llvm-6502/test/CodeGen/NVPTX
Justin Holewinski 7eacad03ef [NVPTX] Disable vector registers
Vectors were being manually scalarized by the backend.  Instead,
let the target-independent code do all of the work.  The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 14:18:49 +00:00
..
annotations.ll
arithmetic-fp-sm10.ll
arithmetic-fp-sm20.ll
arithmetic-int.ll
calling-conv.ll
compare-int.ll
convert-fp.ll
convert-int-sm10.ll
convert-int-sm20.ll
fma-disable.ll
fma.ll
global-ordering.ll
intrin-nocapture.ll
intrinsic-old.ll
intrinsics.ll
ld-addrspace.ll
ld-generic.ll
lit.local.cfg
param-align.ll
pr13291-i1-store.ll
ptx-version-30.ll
ptx-version-31.ll
simple-call.ll
sm-version-10.ll
sm-version-11.ll
sm-version-12.ll
sm-version-13.ll
sm-version-20.ll
sm-version-21.ll
sm-version-30.ll
sm-version-35.ll
st-addrspace.ll
st-generic.ll
tuple-literal.ll
vector-compare.ll
vector-loads.ll [NVPTX] Disable vector registers 2013-02-12 14:18:49 +00:00
vector-select.ll