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928eb49cae
FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
65 lines
3.1 KiB
TableGen
65 lines
3.1 KiB
TableGen
//===- PPCScheduleG3.td - PPC G3 Scheduling Definitions ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the G3 (750) processor.
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//
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//===----------------------------------------------------------------------===//
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def G3Itineraries : ProcessorItineraries<
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[IU1, IU2, FPU1, BPU, SRU, SLU], [
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InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
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InstrItinData<IntMFFS , [InstrStage<1, [FPU1]>]>,
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InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
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InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>,
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InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>,
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InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>,
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InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>,
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InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
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InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
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InstrItinData<BrCR , [InstrStage<1, [SRU]>]>,
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InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>,
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InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>,
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InstrItinData<LdStDCBA , [InstrStage<2, [SLU]>]>,
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InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStGeneral , [InstrStage<2, [SLU]>]>,
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InstrItinData<LdStICBI , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStUX , [InstrStage<2, [SLU]>]>,
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InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>,
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InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>,
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InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>,
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InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>,
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InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
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InstrItinData<LdStSTWCX , [InstrStage<8, [SLU]>]>,
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InstrItinData<LdStSync , [InstrStage<3, [SLU]>]>,
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InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>,
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InstrItinData<SprMFSR , [InstrStage<3, [SRU]>]>,
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InstrItinData<SprMTMSR , [InstrStage<1, [SRU]>]>,
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InstrItinData<SprMTSR , [InstrStage<2, [SRU]>]>,
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InstrItinData<SprTLBSYNC , [InstrStage<3, [SRU]>]>,
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InstrItinData<SprMFCR , [InstrStage<1, [SRU]>]>,
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InstrItinData<SprMFMSR , [InstrStage<1, [SRU]>]>,
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InstrItinData<SprMFSPR , [InstrStage<3, [SRU]>]>,
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InstrItinData<SprMFTB , [InstrStage<3, [SRU]>]>,
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InstrItinData<SprMTSPR , [InstrStage<2, [SRU]>]>,
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InstrItinData<SprMTSRIN , [InstrStage<2, [SRU]>]>,
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InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>,
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InstrItinData<SprSC , [InstrStage<2, [SRU]>]>,
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InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>,
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InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>,
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InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>,
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InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>,
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InstrItinData<FPFused , [InstrStage<2, [FPU1]>]>,
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InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>
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]>;
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