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https://github.com/c64scene-ar/llvm-6502.git
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20ada98de8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128718 91177308-0d34-0410-b5e6-96231b3b80d8
444 lines
15 KiB
C++
444 lines
15 KiB
C++
//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "MipsMachineFunction.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "MipsGenInstrInfo.inc"
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using namespace llvm;
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MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
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: TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImm() && op.getImm() == 0;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned MipsInstrInfo::
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
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(MI->getOpcode() == Mips::LDC1)) {
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if ((MI->getOperand(2).isFI()) && // is a stack slot
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(MI->getOperand(1).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(1)))) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned MipsInstrInfo::
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
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(MI->getOpcode() == Mips::SDC1)) {
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if ((MI->getOperand(2).isFI()) && // is a stack slot
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(MI->getOperand(1).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(1)))) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// insertNoop - If data hazard condition is found insert the target nop
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/// instruction.
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void MipsInstrInfo::
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insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
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{
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DebugLoc DL;
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BuildMI(MBB, MI, DL, get(Mips::NOP));
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}
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void MipsInstrInfo::
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copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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bool DestCPU = Mips::CPURegsRegClass.contains(DestReg);
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bool SrcCPU = Mips::CPURegsRegClass.contains(SrcReg);
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// CPU-CPU is the most common.
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if (DestCPU && SrcCPU) {
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BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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// Copy to CPU from other registers.
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if (DestCPU) {
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if (Mips::CCRRegClass.contains(SrcReg))
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BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (Mips::FGR32RegClass.contains(SrcReg))
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BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (SrcReg == Mips::HI)
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BuildMI(MBB, I, DL, get(Mips::MFHI), DestReg);
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else if (SrcReg == Mips::LO)
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BuildMI(MBB, I, DL, get(Mips::MFLO), DestReg);
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else
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llvm_unreachable("Copy to CPU from invalid register");
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return;
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}
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// Copy to other registers from CPU.
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if (SrcCPU) {
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if (Mips::CCRRegClass.contains(DestReg))
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BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (Mips::FGR32RegClass.contains(DestReg))
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BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (DestReg == Mips::HI)
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BuildMI(MBB, I, DL, get(Mips::MTHI))
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (DestReg == Mips::LO)
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BuildMI(MBB, I, DL, get(Mips::MTLO))
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.addReg(SrcReg, getKillRegState(KillSrc));
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else
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llvm_unreachable("Copy from CPU to invalid register");
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return;
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}
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if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) {
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BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) {
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BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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if (Mips::CCRRegClass.contains(DestReg, SrcReg)) {
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BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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llvm_unreachable("Cannot copy registers");
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}
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void MipsInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
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.addImm(0).addFrameIndex(FI);
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else if (RC == Mips::FGR32RegisterClass)
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BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
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.addImm(0).addFrameIndex(FI);
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else if (RC == Mips::AFGR64RegisterClass) {
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if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
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BuildMI(MBB, I, DL, get(Mips::SDC1))
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.addReg(SrcReg, getKillRegState(isKill))
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.addImm(0).addFrameIndex(FI);
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} else {
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const TargetRegisterInfo *TRI =
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MBB.getParent()->getTarget().getRegisterInfo();
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const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
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BuildMI(MBB, I, DL, get(Mips::SWC1))
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.addReg(SubSet[0], getKillRegState(isKill))
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.addImm(0).addFrameIndex(FI);
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BuildMI(MBB, I, DL, get(Mips::SWC1))
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.addReg(SubSet[1], getKillRegState(isKill))
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.addImm(4).addFrameIndex(FI);
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}
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} else
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llvm_unreachable("Register class not handled!");
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}
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void MipsInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const
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{
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
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else if (RC == Mips::FGR32RegisterClass)
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BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
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else if (RC == Mips::AFGR64RegisterClass) {
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if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
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BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
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} else {
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const TargetRegisterInfo *TRI =
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MBB.getParent()->getTarget().getRegisterInfo();
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const unsigned *SubSet = TRI->getSubRegisters(DestReg);
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BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
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.addImm(0).addFrameIndex(FI);
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BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
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.addImm(4).addFrameIndex(FI);
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}
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} else
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llvm_unreachable("Register class not handled!");
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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static unsigned GetAnalyzableBrOpc(unsigned Opc) {
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return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
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Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
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Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? Opc : 0;
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}
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
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{
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switch (Opc) {
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default: llvm_unreachable("Illegal opcode!");
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case Mips::BEQ : return Mips::BNE;
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case Mips::BNE : return Mips::BEQ;
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case Mips::BGTZ : return Mips::BLEZ;
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case Mips::BGEZ : return Mips::BLTZ;
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case Mips::BLTZ : return Mips::BGEZ;
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case Mips::BLEZ : return Mips::BGTZ;
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case Mips::BC1T : return Mips::BC1F;
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case Mips::BC1F : return Mips::BC1T;
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}
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}
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static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc,
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MachineBasicBlock *&BB,
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SmallVectorImpl<MachineOperand>& Cond) {
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assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
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int NumOp = Inst->getNumExplicitOperands();
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// for both int and fp branches, the last explicit operand is the
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// MBB.
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BB = Inst->getOperand(NumOp-1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(Opc));
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for (int i=0; i<NumOp-1; i++)
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Cond.push_back(Inst->getOperand(i));
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}
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bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const
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{
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MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
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// Skip all the debug instructions.
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while (I != REnd && I->isDebugValue())
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++I;
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if (I == REnd || !isUnpredicatedTerminator(&*I)) {
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// If this block ends with no branches (it just falls through to its succ)
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// just return false, leaving TBB/FBB null.
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TBB = FBB = NULL;
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return false;
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}
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MachineInstr *LastInst = &*I;
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unsigned LastOpc = LastInst->getOpcode();
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// Not an analyzable branch (must be an indirect jump).
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if (!GetAnalyzableBrOpc(LastOpc))
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return true;
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// Get the second to last instruction in the block.
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unsigned SecondLastOpc = 0;
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MachineInstr *SecondLastInst = NULL;
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if (++I != REnd) {
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SecondLastInst = &*I;
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SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
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// Not an analyzable branch (must be an indirect jump).
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if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
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return true;
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}
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// If there is only one terminator instruction, process it.
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if (!SecondLastOpc) {
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// Unconditional branch
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if (LastOpc == Mips::J) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// Conditional branch
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AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
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return false;
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}
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// If we reached here, there are two branches.
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// If there are three terminators, we don't know what sort of block this is.
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if (++I != REnd && isUnpredicatedTerminator(&*I))
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return true;
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// If second to last instruction is an unconditional branch,
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// analyze it and remove the last instruction.
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if (SecondLastOpc == Mips::J) {
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// Return if the last instruction cannot be removed.
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if (!AllowModify)
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return true;
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TBB = SecondLastInst->getOperand(0).getMBB();
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LastInst->eraseFromParent();
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return false;
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}
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// Conditional branch followed by an unconditional branch.
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// The last one must be unconditional.
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if (LastOpc != Mips::J)
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return true;
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AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB, DebugLoc DL,
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const SmallVectorImpl<MachineOperand>& Cond)
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const {
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unsigned Opc = Cond[0].getImm();
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const TargetInstrDesc &TID = get(Opc);
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MachineInstrBuilder MIB = BuildMI(&MBB, DL, TID);
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for (unsigned i = 1; i < Cond.size(); ++i)
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MIB.addReg(Cond[i].getReg());
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MIB.addMBB(TBB);
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}
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unsigned MipsInstrInfo::
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InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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// # of condition operands:
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// Unconditional branches: 0
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// Floating point branches: 1 (opc)
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// Int BranchZero: 2 (opc, reg)
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// Int Branch: 3 (opc, reg0, reg1)
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assert((Cond.size() <= 3) &&
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"# of Mips branch conditions must be <= 3!");
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// Two-way Conditional branch.
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if (FBB) {
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BuildCondBr(MBB, TBB, DL, Cond);
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BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB);
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return 2;
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}
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// One way branch.
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// Unconditional branch.
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if (Cond.empty())
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BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB);
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else // Conditional branch.
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BuildCondBr(MBB, TBB, DL, Cond);
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return 1;
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}
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unsigned MipsInstrInfo::
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RemoveBranch(MachineBasicBlock &MBB) const
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{
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MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
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MachineBasicBlock::reverse_iterator FirstBr;
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unsigned removed;
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// Skip all the debug instructions.
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while (I != REnd && I->isDebugValue())
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++I;
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FirstBr = I;
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// Up to 2 branches are removed.
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// Note that indirect branches are not removed.
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for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
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if (!GetAnalyzableBrOpc(I->getOpcode()))
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break;
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MBB.erase(I.base(), FirstBr.base());
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return removed;
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}
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/// ReverseBranchCondition - Return the inverse opcode of the
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/// specified Branch instruction.
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bool MipsInstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
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{
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assert( (Cond.size() && Cond.size() <= 3) &&
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"Invalid Mips branch condition!");
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Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
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return false;
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}
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/// getGlobalBaseReg - Return a virtual register initialized with the
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/// the global base register value. Output instructions required to
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/// initialize the register in the function entry block, if necessary.
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///
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unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
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MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
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unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
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if (GlobalBaseReg != 0)
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return GlobalBaseReg;
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = MF->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
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BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
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GlobalBaseReg).addReg(Mips::GP);
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RegInfo.addLiveIn(Mips::GP);
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MipsFI->setGlobalBaseReg(GlobalBaseReg);
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return GlobalBaseReg;
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}
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