Colin LeMahieu 9f3b3bca89 [Hexagon] Adding JR class predicated call reg instructions. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223933 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-10 18:24:16 +00:00
..
AArch64	Update AArch64 ELF relocations to ABI 1.0	2014-11-26 10:49:18 +00:00
ARM	Fix modified immediate bug reported by MC Hammer.	2014-12-09 13:14:58 +00:00
AsmParser	MC: AsmLexer: handle multi-character CommentStrings correctly	2014-08-14 02:51:43 +00:00
COFF	MC, COFF: Use relocations for function references inside the section	2014-11-11 08:43:57 +00:00
Disassembler	[Hexagon] Adding JR class predicated call reg instructions.	2014-12-10 18:24:16 +00:00
ELF	Commit back the correct bits of r222760 (was r222538).	2014-11-27 17:13:56 +00:00
Hexagon	[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings.	2014-12-09 18:16:49 +00:00
MachO	Don't produce relocations for a difference in a section with no symbols.	2014-11-04 22:10:33 +00:00
Markup
Mips	The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.	2014-12-01 11:12:04 +00:00
PowerPC	[PowerPC] Add asm support for cache-inhibited ld/st instructions	2014-11-30 10:15:56 +00:00
R600	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
Sparc	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	Exclude known and bugzilled failures from UBSan bootstrap	2014-09-17 20:17:52 +00:00
X86	[AVX512] Added VPBROADCAST{BWDQ} (Load with Broadcast Integer Data from General Purpose Register) encodings for AVX512-BW/VL subsets	2014-12-09 16:38:41 +00:00