llvm-6502/test/CodeGen
Cameron Zwarich c0e6d780cd Add a ARM-specific SD node for VBSL so that forms with a constant first operand
can be recognized. This fixes <rdar://problem/9183078>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:01:21 +00:00
..
Alpha
ARM Add a ARM-specific SD node for VBSL so that forms with a constant first operand 2011-03-30 23:01:21 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic
MBlaze
Mips
MSP430
PowerPC
PTX
SPARC
SystemZ
Thumb
Thumb2 Fix the bfi handling for or (and a mask) (and b mask). We need the two 2011-03-26 01:21:03 +00:00
X86 Reduce test case. 2011-03-29 02:18:54 +00:00
XCore