llvm-6502/lib/Target/Hexagon/HexagonTargetMachine.h
Andrew Trick 061efcfb3e TargetPassConfig: confine the MC configuration to TargetMachine.
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.

Sorry for the target header churn. Attempting to stabilize them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-04 02:56:59 +00:00

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//=-- HexagonTargetMachine.h - Define TargetMachine for Hexagon ---*- C++ -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the Hexagon specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
#ifndef HexagonTARGETMACHINE_H
#define HexagonTARGETMACHINE_H
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetData.h"
#include "HexagonInstrInfo.h"
#include "HexagonSubtarget.h"
#include "HexagonISelLowering.h"
#include "HexagonSelectionDAGInfo.h"
#include "HexagonFrameLowering.h"
namespace llvm {
class Module;
class HexagonTargetMachine : public LLVMTargetMachine {
const TargetData DataLayout; // Calculates type size & alignment.
HexagonSubtarget Subtarget;
HexagonInstrInfo InstrInfo;
HexagonTargetLowering TLInfo;
HexagonSelectionDAGInfo TSInfo;
HexagonFrameLowering FrameLowering;
const InstrItineraryData* InstrItins;
public:
HexagonTargetMachine(const Target &T, StringRef TT,StringRef CPU,
StringRef FS, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL);
virtual const HexagonInstrInfo *getInstrInfo() const {
return &InstrInfo;
}
virtual const HexagonSubtarget *getSubtargetImpl() const {
return &Subtarget;
}
virtual const HexagonRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
virtual const InstrItineraryData* getInstrItineraryData() const {
return InstrItins;
}
virtual const HexagonTargetLowering* getTargetLowering() const {
return &TLInfo;
}
virtual const HexagonFrameLowering* getFrameLowering() const {
return &FrameLowering;
}
virtual const HexagonSelectionDAGInfo* getSelectionDAGInfo() const {
return &TSInfo;
}
virtual const TargetData *getTargetData() const { return &DataLayout; }
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration.
virtual bool addPassesForOptimizations(PassManagerBase &PM);
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
};
extern bool flag_aligned_memcpy;
} // end namespace llvm
#endif