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https://github.com/c64scene-ar/llvm-6502.git
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a430cb613b
and mips16 on a per function basis. Because this patch is somewhat involved I have provide an overview of the key pieces of it. The patch is written so as to not change the behavior of the non mixed mode. We have tested this a lot but it is something new to switch subtargets so we don't want any chance of regression in the mainline compiler until we have more confidence in this. Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1. For that reason there are derived versions of the register info, frame info, instruction info and instruction selection classes. Now we register three separate passes for instruction selection. One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and MipsSEISelDAGToDAG.cpp). When the ModuleISel pass runs, it determines if there is a need to switch subtargets and if so, the owning pointers in MipsTargetMachine are appropriately changed. When 16Isel or SEIsel is run, they will return immediately without doing any work if the current subtarget mode does not apply to them. In addition, MipsAsmPrinter needs to be reset on a function basis. The pass BasicTargetTransformInfo is substituted with a null pass since the pass is immutable and really needs to be a function pass for it to be used with changing subtargets. This will be fixed in a follow on patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179118 91177308-0d34-0410-b5e6-96231b3b80d8
120 lines
3.7 KiB
C++
120 lines
3.7 KiB
C++
//===-- MipsTargetMachine.h - Define TargetMachine for Mips -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Mips specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSTARGETMACHINE_H
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#define MIPSTARGETMACHINE_H
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#include "MipsFrameLowering.h"
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#include "MipsISelLowering.h"
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#include "MipsInstrInfo.h"
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#include "MipsJITInfo.h"
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#include "MipsSelectionDAGInfo.h"
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#include "MipsSubtarget.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class formatted_raw_ostream;
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class MipsRegisterInfo;
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class MipsTargetMachine : public LLVMTargetMachine {
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MipsSubtarget Subtarget;
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const DataLayout DL; // Calculates type size & alignment
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OwningPtr<const MipsInstrInfo> InstrInfo;
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OwningPtr<const MipsFrameLowering> FrameLowering;
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OwningPtr<const MipsTargetLowering> TLInfo;
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OwningPtr<const MipsInstrInfo> InstrInfo16;
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OwningPtr<const MipsFrameLowering> FrameLowering16;
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OwningPtr<const MipsTargetLowering> TLInfo16;
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OwningPtr<const MipsInstrInfo> InstrInfoSE;
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OwningPtr<const MipsFrameLowering> FrameLoweringSE;
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OwningPtr<const MipsTargetLowering> TLInfoSE;
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MipsSelectionDAGInfo TSInfo;
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MipsJITInfo JITInfo;
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public:
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MipsTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool isLittle);
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virtual ~MipsTargetMachine() {}
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virtual void addAnalysisPasses(PassManagerBase &PM);
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virtual const MipsInstrInfo *getInstrInfo() const
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{ return InstrInfo.get(); }
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virtual const TargetFrameLowering *getFrameLowering() const
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{ return FrameLowering.get(); }
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virtual const MipsSubtarget *getSubtargetImpl() const
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{ return &Subtarget; }
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virtual const DataLayout *getDataLayout() const
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{ return &DL;}
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virtual MipsJITInfo *getJITInfo()
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{ return &JITInfo; }
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virtual const MipsRegisterInfo *getRegisterInfo() const {
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return &InstrInfo->getRegisterInfo();
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}
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virtual const MipsTargetLowering *getTargetLowering() const {
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return TLInfo.get();
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}
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virtual const MipsSelectionDAGInfo* getSelectionDAGInfo() const {
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return &TSInfo;
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}
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// Pass Pipeline Configuration
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virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
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virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE);
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// Set helper classes
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void setHelperClassesMips16();
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void setHelperClassesMipsSE();
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};
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/// MipsebTargetMachine - Mips32/64 big endian target machine.
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///
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class MipsebTargetMachine : public MipsTargetMachine {
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virtual void anchor();
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public:
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MipsebTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// MipselTargetMachine - Mips32/64 little endian target machine.
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///
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class MipselTargetMachine : public MipsTargetMachine {
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virtual void anchor();
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public:
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MipselTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // End llvm namespace
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#endif
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