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https://github.com/c64scene-ar/llvm-6502.git
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f93b863066
them as machine instructions. Directives ".set noat" and ".set at" are now emitted only at the beginning and end of a function except in the case where they are emitted to enclose .cpload with an immediate operand that doesn't fit in 16-bit field or unaligned load/stores. Also, make the following changes: - Remove function isUnalignedLoadStore and use a switch-case statement to determine whether an instruction is an unaligned load or store. - Define helper function CreateMCInst which generates an instance of an MCInst from an opcode and a list of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153552 91177308-0d34-0410-b5e6-96231b3b80d8
344 lines
12 KiB
C++
344 lines
12 KiB
C++
//===-- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower Mips MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsMCInstLower.h"
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#include "MipsAsmPrinter.h"
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#include "MipsInstrInfo.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/Mangler.h"
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using namespace llvm;
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MipsMCInstLower::MipsMCInstLower(MipsAsmPrinter &asmprinter)
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: AsmPrinter(asmprinter) {}
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void MipsMCInstLower::Initialize(Mangler *M, MCContext* C) {
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Mang = M;
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Ctx = C;
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}
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MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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MachineOperandType MOTy,
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unsigned Offset) const {
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MCSymbolRefExpr::VariantKind Kind;
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const MCSymbol *Symbol;
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switch(MO.getTargetFlags()) {
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default: llvm_unreachable("Invalid target flag!");
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case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break;
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case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break;
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case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break;
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case MipsII::MO_GOT16: Kind = MCSymbolRefExpr::VK_Mips_GOT16; break;
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case MipsII::MO_GOT: Kind = MCSymbolRefExpr::VK_Mips_GOT; break;
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case MipsII::MO_ABS_HI: Kind = MCSymbolRefExpr::VK_Mips_ABS_HI; break;
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case MipsII::MO_ABS_LO: Kind = MCSymbolRefExpr::VK_Mips_ABS_LO; break;
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case MipsII::MO_TLSGD: Kind = MCSymbolRefExpr::VK_Mips_TLSGD; break;
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case MipsII::MO_TLSLDM: Kind = MCSymbolRefExpr::VK_Mips_TLSLDM; break;
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case MipsII::MO_DTPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_HI; break;
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case MipsII::MO_DTPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_LO; break;
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case MipsII::MO_GOTTPREL: Kind = MCSymbolRefExpr::VK_Mips_GOTTPREL; break;
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case MipsII::MO_TPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_TPREL_HI; break;
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case MipsII::MO_TPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_TPREL_LO; break;
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case MipsII::MO_GPOFF_HI: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_HI; break;
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case MipsII::MO_GPOFF_LO: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_LO; break;
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case MipsII::MO_GOT_DISP: Kind = MCSymbolRefExpr::VK_Mips_GOT_DISP; break;
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case MipsII::MO_GOT_PAGE: Kind = MCSymbolRefExpr::VK_Mips_GOT_PAGE; break;
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case MipsII::MO_GOT_OFST: Kind = MCSymbolRefExpr::VK_Mips_GOT_OFST; break;
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}
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switch (MOTy) {
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case MachineOperand::MO_MachineBasicBlock:
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Symbol = MO.getMBB()->getSymbol();
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break;
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case MachineOperand::MO_GlobalAddress:
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Symbol = Mang->getSymbol(MO.getGlobal());
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break;
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case MachineOperand::MO_BlockAddress:
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Symbol = AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress());
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break;
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case MachineOperand::MO_ExternalSymbol:
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Symbol = AsmPrinter.GetExternalSymbolSymbol(MO.getSymbolName());
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break;
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case MachineOperand::MO_JumpTableIndex:
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Symbol = AsmPrinter.GetJTISymbol(MO.getIndex());
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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Symbol = AsmPrinter.GetCPISymbol(MO.getIndex());
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if (MO.getOffset())
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Offset += MO.getOffset();
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break;
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default:
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llvm_unreachable("<unknown operand type>");
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}
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const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, *Ctx);
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if (!Offset)
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return MCOperand::CreateExpr(MCSym);
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// Assume offset is never negative.
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assert(Offset > 0);
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const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, *Ctx);
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const MCBinaryExpr *AddExpr = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, *Ctx);
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return MCOperand::CreateExpr(AddExpr);
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}
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static void CreateMCInst(MCInst& Inst, unsigned Opc, const MCOperand& Opnd0,
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const MCOperand& Opnd1,
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const MCOperand& Opnd2 = MCOperand()) {
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Inst.setOpcode(Opc);
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Inst.addOperand(Opnd0);
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Inst.addOperand(Opnd1);
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if (Opnd2.isValid())
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Inst.addOperand(Opnd2);
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}
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// Lower ".cpload $reg" to
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// "lui $gp, %hi(_gp_disp)"
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// "addiu $gp, $gp, %lo(_gp_disp)"
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// "addu $gp, $gp, $t9"
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void MipsMCInstLower::LowerCPLOAD(SmallVector<MCInst, 4>& MCInsts) {
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MCOperand GPReg = MCOperand::CreateReg(Mips::GP);
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MCOperand T9Reg = MCOperand::CreateReg(Mips::T9);
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StringRef SymName("_gp_disp");
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const MCSymbol *Sym = Ctx->GetOrCreateSymbol(SymName);
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const MCSymbolRefExpr *MCSym;
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MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_HI, *Ctx);
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MCOperand SymHi = MCOperand::CreateExpr(MCSym);
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MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_LO, *Ctx);
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MCOperand SymLo = MCOperand::CreateExpr(MCSym);
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MCInsts.resize(3);
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CreateMCInst(MCInsts[0], Mips::LUi, GPReg, SymHi);
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CreateMCInst(MCInsts[1], Mips::ADDiu, GPReg, GPReg, SymLo);
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CreateMCInst(MCInsts[2], Mips::ADDu, GPReg, GPReg, T9Reg);
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}
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// Lower ".cprestore offset" to "sw $gp, offset($sp)".
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void MipsMCInstLower::LowerCPRESTORE(int64_t Offset,
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SmallVector<MCInst, 4>& MCInsts) {
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assert(isInt<32>(Offset) && (Offset >= 0) &&
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"Imm operand of .cprestore must be a non-negative 32-bit value.");
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MCOperand SPReg = MCOperand::CreateReg(Mips::SP), BaseReg = SPReg;
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MCOperand GPReg = MCOperand::CreateReg(Mips::GP);
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if (!isInt<16>(Offset)) {
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unsigned Hi = ((Offset + 0x8000) >> 16) & 0xffff;
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Offset &= 0xffff;
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MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
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BaseReg = ATReg;
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// lui at,hi
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// addu at,at,sp
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MCInsts.resize(2);
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CreateMCInst(MCInsts[0], Mips::LUi, ATReg, MCOperand::CreateImm(Hi));
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CreateMCInst(MCInsts[1], Mips::ADDu, ATReg, ATReg, SPReg);
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}
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MCInst Sw;
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CreateMCInst(Sw, Mips::SW, GPReg, BaseReg, MCOperand::CreateImm(Offset));
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MCInsts.push_back(Sw);
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}
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MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO,
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unsigned offset) const {
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MachineOperandType MOTy = MO.getType();
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switch (MOTy) {
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default: llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit()) break;
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return MCOperand::CreateReg(MO.getReg());
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case MachineOperand::MO_Immediate:
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return MCOperand::CreateImm(MO.getImm() + offset);
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case MachineOperand::MO_MachineBasicBlock:
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case MachineOperand::MO_GlobalAddress:
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case MachineOperand::MO_ExternalSymbol:
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case MachineOperand::MO_JumpTableIndex:
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case MachineOperand::MO_ConstantPoolIndex:
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case MachineOperand::MO_BlockAddress:
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return LowerSymbolOperand(MO, MOTy, offset);
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case MachineOperand::MO_RegisterMask:
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break;
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}
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return MCOperand();
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}
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void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp = LowerOperand(MO);
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if (MCOp.isValid())
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OutMI.addOperand(MCOp);
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}
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}
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void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
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SmallVector<MCInst,
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4>& MCInsts) {
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unsigned Opc = MI->getOpcode();
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MCInst Instr1, Instr2, Instr3, Move;
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bool TwoInstructions = false;
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assert(MI->getNumOperands() == 3);
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assert(MI->getOperand(0).isReg());
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assert(MI->getOperand(1).isReg());
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MCOperand Target = LowerOperand(MI->getOperand(0));
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MCOperand Base = LowerOperand(MI->getOperand(1));
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MCOperand ATReg = MCOperand::CreateReg(Mips::AT);
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MCOperand ZeroReg = MCOperand::CreateReg(Mips::ZERO);
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MachineOperand UnLoweredName = MI->getOperand(2);
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MCOperand Name = LowerOperand(UnLoweredName);
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Move.setOpcode(Mips::ADDu);
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Move.addOperand(Target);
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Move.addOperand(ATReg);
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Move.addOperand(ZeroReg);
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switch (Opc) {
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case Mips::ULW: {
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// FIXME: only works for little endian right now
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MCOperand AdjName = LowerOperand(UnLoweredName, 3);
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if (Base.getReg() == (Target.getReg())) {
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Instr1.setOpcode(Mips::LWL);
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Instr1.addOperand(ATReg);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::LWR);
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Instr2.addOperand(ATReg);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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Instr3 = Move;
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} else {
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TwoInstructions = true;
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Instr1.setOpcode(Mips::LWL);
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Instr1.addOperand(Target);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::LWR);
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Instr2.addOperand(Target);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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}
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break;
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}
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case Mips::ULHu: {
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// FIXME: only works for little endian right now
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MCOperand AdjName = LowerOperand(UnLoweredName, 1);
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Instr1.setOpcode(Mips::LBu);
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Instr1.addOperand(ATReg);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::LBu);
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Instr2.addOperand(Target);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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Instr3.setOpcode(Mips::INS);
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Instr3.addOperand(Target);
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Instr3.addOperand(ATReg);
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Instr3.addOperand(MCOperand::CreateImm(0x8));
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Instr3.addOperand(MCOperand::CreateImm(0x18));
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break;
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}
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case Mips::USW: {
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// FIXME: only works for little endian right now
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assert (Base.getReg() != Target.getReg());
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TwoInstructions = true;
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MCOperand AdjName = LowerOperand(UnLoweredName, 3);
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Instr1.setOpcode(Mips::SWL);
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Instr1.addOperand(Target);
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Instr1.addOperand(Base);
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Instr1.addOperand(AdjName);
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Instr2.setOpcode(Mips::SWR);
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Instr2.addOperand(Target);
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Instr2.addOperand(Base);
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Instr2.addOperand(Name);
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break;
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}
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case Mips::USH: {
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MCOperand AdjName = LowerOperand(UnLoweredName, 1);
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Instr1.setOpcode(Mips::SB);
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Instr1.addOperand(Target);
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Instr1.addOperand(Base);
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Instr1.addOperand(Name);
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Instr2.setOpcode(Mips::SRL);
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Instr2.addOperand(ATReg);
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Instr2.addOperand(Target);
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Instr2.addOperand(MCOperand::CreateImm(8));
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Instr3.setOpcode(Mips::SB);
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Instr3.addOperand(ATReg);
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Instr3.addOperand(Base);
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Instr3.addOperand(AdjName);
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break;
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}
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default:
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// FIXME: need to add others
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llvm_unreachable("unaligned instruction not processed");
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}
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MCInsts.push_back(Instr1);
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MCInsts.push_back(Instr2);
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if (!TwoInstructions) MCInsts.push_back(Instr3);
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}
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// Convert
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// "setgp01 $reg"
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// to
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// "lui $reg, %hi(_gp_disp)"
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// "addiu $reg, $reg, %lo(_gp_disp)"
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void MipsMCInstLower::LowerSETGP01(const MachineInstr *MI,
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SmallVector<MCInst, 4>& MCInsts) {
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const MachineOperand &MO = MI->getOperand(0);
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assert(MO.isReg());
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MCOperand RegOpnd = MCOperand::CreateReg(MO.getReg());
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StringRef SymName("_gp_disp");
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const MCSymbol *Sym = Ctx->GetOrCreateSymbol(SymName);
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const MCSymbolRefExpr *MCSym;
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MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_HI, *Ctx);
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MCOperand SymHi = MCOperand::CreateExpr(MCSym);
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MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_LO, *Ctx);
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MCOperand SymLo = MCOperand::CreateExpr(MCSym);
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MCInsts.resize(2);
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CreateMCInst(MCInsts[0], Mips::LUi, RegOpnd, SymHi);
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CreateMCInst(MCInsts[1], Mips::ADDiu, RegOpnd, RegOpnd, SymLo);
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}
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