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6584d94610
Weak symbols cannot use the small code model's usual ADRP sequences since the instruction simply may not be able to encode a value of 0. This redirects them to use the GOT, which hopefully linkers are able to cope with even in the static relocation model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205426 91177308-0d34-0410-b5e6-96231b3b80d8
101 lines
3.9 KiB
C++
101 lines
3.9 KiB
C++
//===-- ARM64Subtarget.cpp - ARM64 Subtarget Information --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARM64 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM64InstrInfo.h"
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#include "ARM64Subtarget.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_TARGET_DESC
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#include "ARM64GenSubtargetInfo.inc"
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using namespace llvm;
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ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS)
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: ARM64GenSubtargetInfo(TT, CPU, FS), HasZeroCycleRegMove(false),
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HasZeroCycleZeroing(false), CPUString(CPU), TargetTriple(TT) {
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// Determine default and user-specified characteristics
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if (CPUString.empty())
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// We default to Cyclone for now.
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CPUString = "cyclone";
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ParseSubtargetFeatures(CPUString, FS);
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}
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/// ClassifyGlobalReference - Find the target operand flags that describe
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/// how a global value should be referenced for the current subtarget.
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unsigned char
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ARM64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
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const TargetMachine &TM) const {
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// Determine whether this is a reference to a definition or a declaration.
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// Materializable GVs (in JIT lazy compilation mode) do not require an extra
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// load from stub.
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bool isDecl = GV->hasAvailableExternallyLinkage();
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if (GV->isDeclaration() && !GV->isMaterializable())
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isDecl = true;
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// MachO large model always goes via a GOT, simply to get a single 8-byte
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// absolute relocation on all global addresses.
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if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
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return ARM64II::MO_GOT;
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// The small code mode's direct accesses use ADRP, which cannot necessarily
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// produce the value 0 (if the code is above 4GB). Therefore they must use the
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// GOT.
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if (TM.getCodeModel() == CodeModel::Small && GV->isWeakForLinker() && isDecl)
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return ARM64II::MO_GOT;
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// If symbol visibility is hidden, the extra load is not needed if
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// the symbol is definitely defined in the current translation unit.
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// The handling of non-hidden symbols in PIC mode is rather target-dependent:
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// + On MachO, if the symbol is defined in this module the GOT can be
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// skipped.
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// + On ELF, the R_AARCH64_COPY relocation means that even symbols actually
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// defined could end up in unexpected places. Use a GOT.
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if (TM.getRelocationModel() != Reloc::Static && GV->hasDefaultVisibility()) {
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if (isTargetMachO())
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return (isDecl || GV->isWeakForLinker()) ? ARM64II::MO_GOT
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: ARM64II::MO_NO_FLAG;
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else
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return ARM64II::MO_GOT;
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}
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return ARM64II::MO_NO_FLAG;
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}
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/// This function returns the name of a function which has an interface
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/// like the non-standard bzero function, if such a function exists on
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/// the current subtarget and it is considered prefereable over
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/// memset with zero passed as the second argument. Otherwise it
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/// returns null.
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const char *ARM64Subtarget::getBZeroEntry() const {
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// At the moment, always prefer bzero.
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return "bzero";
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}
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void ARM64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
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MachineInstr *begin, MachineInstr *end,
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unsigned NumRegionInstrs) const {
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// LNT run (at least on Cyclone) showed reasonably significant gains for
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// bi-directional scheduling. 253.perlbmk.
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = false;
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}
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