mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 05:29:47 +00:00
fd506efec6
is used in cases where global symbols are directly represented in the GOT and we use an offset into the global offset table. This patch adds direct object support for R_MIPS_GOT_DISP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160183 91177308-0d34-0410-b5e6-96231b3b80d8
302 lines
11 KiB
C++
302 lines
11 KiB
C++
//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file implements the MipsMCCodeEmitter class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
#define DEBUG_TYPE "mccodeemitter"
|
|
#include "MCTargetDesc/MipsBaseInfo.h"
|
|
#include "MCTargetDesc/MipsFixupKinds.h"
|
|
#include "MCTargetDesc/MipsMCTargetDesc.h"
|
|
#include "llvm/ADT/APFloat.h"
|
|
#include "llvm/ADT/Statistic.h"
|
|
#include "llvm/MC/MCCodeEmitter.h"
|
|
#include "llvm/MC/MCExpr.h"
|
|
#include "llvm/MC/MCInst.h"
|
|
#include "llvm/MC/MCInstrInfo.h"
|
|
#include "llvm/MC/MCRegisterInfo.h"
|
|
#include "llvm/MC/MCSubtargetInfo.h"
|
|
#include "llvm/Support/raw_ostream.h"
|
|
|
|
using namespace llvm;
|
|
|
|
namespace {
|
|
class MipsMCCodeEmitter : public MCCodeEmitter {
|
|
MipsMCCodeEmitter(const MipsMCCodeEmitter &); // DO NOT IMPLEMENT
|
|
void operator=(const MipsMCCodeEmitter &); // DO NOT IMPLEMENT
|
|
const MCInstrInfo &MCII;
|
|
const MCSubtargetInfo &STI;
|
|
MCContext &Ctx;
|
|
bool IsLittleEndian;
|
|
|
|
public:
|
|
MipsMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
|
|
MCContext &ctx, bool IsLittle) :
|
|
MCII(mcii), STI(sti) , Ctx(ctx), IsLittleEndian(IsLittle) {}
|
|
|
|
~MipsMCCodeEmitter() {}
|
|
|
|
void EmitByte(unsigned char C, raw_ostream &OS) const {
|
|
OS << (char)C;
|
|
}
|
|
|
|
void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
|
|
// Output the instruction encoding in little endian byte order.
|
|
for (unsigned i = 0; i < Size; ++i) {
|
|
unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
|
|
EmitByte((Val >> Shift) & 0xff, OS);
|
|
}
|
|
}
|
|
|
|
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
|
SmallVectorImpl<MCFixup> &Fixups) const;
|
|
|
|
// getBinaryCodeForInstr - TableGen'erated function for getting the
|
|
// binary encoding for an instruction.
|
|
uint64_t getBinaryCodeForInstr(const MCInst &MI,
|
|
SmallVectorImpl<MCFixup> &Fixups) const;
|
|
|
|
// getBranchJumpOpValue - Return binary encoding of the jump
|
|
// target operand. If the machine operand requires relocation,
|
|
// record the relocation and return zero.
|
|
unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups) const;
|
|
|
|
// getBranchTargetOpValue - Return binary encoding of the branch
|
|
// target operand. If the machine operand requires relocation,
|
|
// record the relocation and return zero.
|
|
unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups) const;
|
|
|
|
// getMachineOpValue - Return binary encoding of operand. If the machin
|
|
// operand requires relocation, record the relocation and return zero.
|
|
unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
|
|
SmallVectorImpl<MCFixup> &Fixups) const;
|
|
|
|
unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups) const;
|
|
unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups) const;
|
|
unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups) const;
|
|
|
|
}; // class MipsMCCodeEmitter
|
|
} // namespace
|
|
|
|
MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
|
|
const MCRegisterInfo &MRI,
|
|
const MCSubtargetInfo &STI,
|
|
MCContext &Ctx)
|
|
{
|
|
return new MipsMCCodeEmitter(MCII, STI, Ctx, false);
|
|
}
|
|
|
|
MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
|
|
const MCRegisterInfo &MRI,
|
|
const MCSubtargetInfo &STI,
|
|
MCContext &Ctx)
|
|
{
|
|
return new MipsMCCodeEmitter(MCII, STI, Ctx, true);
|
|
}
|
|
|
|
/// EncodeInstruction - Emit the instruction.
|
|
/// Size the instruction (currently only 4 bytes
|
|
void MipsMCCodeEmitter::
|
|
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
|
SmallVectorImpl<MCFixup> &Fixups) const
|
|
{
|
|
uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
|
|
|
|
// Check for unimplemented opcodes.
|
|
// Unfortunately in MIPS both NOT and SLL will come in with Binary == 0
|
|
// so we have to special check for them.
|
|
unsigned Opcode = MI.getOpcode();
|
|
if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
|
|
llvm_unreachable("unimplemented opcode in EncodeInstruction()");
|
|
|
|
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
|
|
uint64_t TSFlags = Desc.TSFlags;
|
|
|
|
// Pseudo instructions don't get encoded and shouldn't be here
|
|
// in the first place!
|
|
if ((TSFlags & MipsII::FormMask) == MipsII::Pseudo)
|
|
llvm_unreachable("Pseudo opcode found in EncodeInstruction()");
|
|
|
|
// For now all instructions are 4 bytes
|
|
int Size = 4; // FIXME: Have Desc.getSize() return the correct value!
|
|
|
|
EmitInstruction(Binary, Size, OS);
|
|
}
|
|
|
|
/// getBranchTargetOpValue - Return binary encoding of the branch
|
|
/// target operand. If the machine operand requires relocation,
|
|
/// record the relocation and return zero.
|
|
unsigned MipsMCCodeEmitter::
|
|
getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
assert(MO.isExpr() && "getBranchTargetOpValue expects only expressions");
|
|
|
|
const MCExpr *Expr = MO.getExpr();
|
|
Fixups.push_back(MCFixup::Create(0, Expr,
|
|
MCFixupKind(Mips::fixup_Mips_PC16)));
|
|
return 0;
|
|
}
|
|
|
|
/// getJumpTargetOpValue - Return binary encoding of the jump
|
|
/// target operand. If the machine operand requires relocation,
|
|
/// record the relocation and return zero.
|
|
unsigned MipsMCCodeEmitter::
|
|
getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
assert(MO.isExpr() && "getJumpTargetOpValue expects only expressions");
|
|
|
|
const MCExpr *Expr = MO.getExpr();
|
|
Fixups.push_back(MCFixup::Create(0, Expr,
|
|
MCFixupKind(Mips::fixup_Mips_26)));
|
|
return 0;
|
|
}
|
|
|
|
/// getMachineOpValue - Return binary encoding of operand. If the machine
|
|
/// operand requires relocation, record the relocation and return zero.
|
|
unsigned MipsMCCodeEmitter::
|
|
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
if (MO.isReg()) {
|
|
unsigned Reg = MO.getReg();
|
|
unsigned RegNo = getMipsRegisterNumbering(Reg);
|
|
return RegNo;
|
|
} else if (MO.isImm()) {
|
|
return static_cast<unsigned>(MO.getImm());
|
|
} else if (MO.isFPImm()) {
|
|
return static_cast<unsigned>(APFloat(MO.getFPImm())
|
|
.bitcastToAPInt().getHiBits(32).getLimitedValue());
|
|
}
|
|
|
|
// MO must be an Expr.
|
|
assert(MO.isExpr());
|
|
|
|
const MCExpr *Expr = MO.getExpr();
|
|
MCExpr::ExprKind Kind = Expr->getKind();
|
|
|
|
if (Kind == MCExpr::Binary) {
|
|
Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS();
|
|
Kind = Expr->getKind();
|
|
}
|
|
|
|
assert (Kind == MCExpr::SymbolRef);
|
|
|
|
Mips::Fixups FixupKind = Mips::Fixups(0);
|
|
|
|
switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
|
|
default: llvm_unreachable("Unknown fixup kind!");
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
|
|
FixupKind = Mips::fixup_Mips_GPOFF_HI;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
|
|
FixupKind = Mips::fixup_Mips_GPOFF_LO;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
|
|
FixupKind = Mips::fixup_Mips_GOT_PAGE;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_GOT_OFST :
|
|
FixupKind = Mips::fixup_Mips_GOT_OFST;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_GOT_DISP :
|
|
FixupKind = Mips::fixup_Mips_GOT_DISP;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_GPREL:
|
|
FixupKind = Mips::fixup_Mips_GPREL16;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_GOT_CALL:
|
|
FixupKind = Mips::fixup_Mips_CALL16;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_GOT16:
|
|
FixupKind = Mips::fixup_Mips_GOT_Global;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_GOT:
|
|
FixupKind = Mips::fixup_Mips_GOT_Local;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_ABS_HI:
|
|
FixupKind = Mips::fixup_Mips_HI16;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_ABS_LO:
|
|
FixupKind = Mips::fixup_Mips_LO16;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_TLSGD:
|
|
FixupKind = Mips::fixup_Mips_TLSGD;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_TLSLDM:
|
|
FixupKind = Mips::fixup_Mips_TLSLDM;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
|
|
FixupKind = Mips::fixup_Mips_DTPREL_HI;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
|
|
FixupKind = Mips::fixup_Mips_DTPREL_LO;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_GOTTPREL:
|
|
FixupKind = Mips::fixup_Mips_GOTTPREL;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_TPREL_HI:
|
|
FixupKind = Mips::fixup_Mips_TPREL_HI;
|
|
break;
|
|
case MCSymbolRefExpr::VK_Mips_TPREL_LO:
|
|
FixupKind = Mips::fixup_Mips_TPREL_LO;
|
|
break;
|
|
} // switch
|
|
|
|
Fixups.push_back(MCFixup::Create(0, MO.getExpr(), MCFixupKind(FixupKind)));
|
|
|
|
// All of the information is in the fixup.
|
|
return 0;
|
|
}
|
|
|
|
/// getMemEncoding - Return binary encoding of memory related operand.
|
|
/// If the offset operand requires relocation, record the relocation.
|
|
unsigned
|
|
MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
// Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
|
|
assert(MI.getOperand(OpNo).isReg());
|
|
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
|
|
unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
|
|
|
|
return (OffBits & 0xFFFF) | RegBits;
|
|
}
|
|
|
|
unsigned
|
|
MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
assert(MI.getOperand(OpNo).isImm());
|
|
unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
|
|
return SizeEncoding - 1;
|
|
}
|
|
|
|
// FIXME: should be called getMSBEncoding
|
|
//
|
|
unsigned
|
|
MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups) const {
|
|
assert(MI.getOperand(OpNo-1).isImm());
|
|
assert(MI.getOperand(OpNo).isImm());
|
|
unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
|
|
unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
|
|
|
|
return Position + Size - 1;
|
|
}
|
|
|
|
#include "MipsGenMCCodeEmitter.inc"
|
|
|