mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 05:29:47 +00:00
MipsSERegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
129 lines
4.2 KiB
C++
129 lines
4.2 KiB
C++
//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the Mips16 implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "Mips16InstrInfo.h"
|
|
#include "MipsTargetMachine.h"
|
|
#include "MipsMachineFunction.h"
|
|
#include "InstPrinter/MipsInstPrinter.h"
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
#include "llvm/Support/ErrorHandling.h"
|
|
#include "llvm/Support/TargetRegistry.h"
|
|
#include "llvm/ADT/STLExtras.h"
|
|
#include "llvm/ADT/StringRef.h"
|
|
|
|
using namespace llvm;
|
|
|
|
Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
|
|
: MipsInstrInfo(tm, /* FIXME: set mips16 unconditional br */ 0),
|
|
RI(*tm.getSubtargetImpl(), *this) {}
|
|
|
|
const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
|
|
return RI;
|
|
}
|
|
|
|
/// isLoadFromStackSlot - If the specified machine instruction is a direct
|
|
/// load from a stack slot, return the virtual or physical register number of
|
|
/// the destination along with the FrameIndex of the loaded stack slot. If
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
/// any side effects other than loading from the stack slot.
|
|
unsigned Mips16InstrInfo::
|
|
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
/// isStoreToStackSlot - If the specified machine instruction is a direct
|
|
/// store to a stack slot, return the virtual or physical register number of
|
|
/// the source reg along with the FrameIndex of the loaded stack slot. If
|
|
/// not, return 0. This predicate must return 0 if the instruction has
|
|
/// any side effects other than storing to the stack slot.
|
|
unsigned Mips16InstrInfo::
|
|
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I, DebugLoc DL,
|
|
unsigned DestReg, unsigned SrcReg,
|
|
bool KillSrc) const {
|
|
unsigned Opc = 0, ZeroReg = 0;
|
|
|
|
if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
|
|
if (Mips::CPURegsRegClass.contains(SrcReg))
|
|
Opc = Mips::Mov32R16;
|
|
}
|
|
|
|
assert(Opc && "Cannot copy registers");
|
|
|
|
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
|
|
|
|
if (DestReg)
|
|
MIB.addReg(DestReg, RegState::Define);
|
|
|
|
if (ZeroReg)
|
|
MIB.addReg(ZeroReg);
|
|
|
|
if (SrcReg)
|
|
MIB.addReg(SrcReg, getKillRegState(KillSrc));
|
|
}
|
|
|
|
void Mips16InstrInfo::
|
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned SrcReg, bool isKill, int FI,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const {
|
|
assert(false && "Implement this function.");
|
|
}
|
|
|
|
void Mips16InstrInfo::
|
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned DestReg, int FI,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const {
|
|
assert(false && "Implement this function.");
|
|
}
|
|
|
|
bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
|
|
MachineBasicBlock &MBB = *MI->getParent();
|
|
|
|
switch(MI->getDesc().getOpcode()) {
|
|
default:
|
|
return false;
|
|
case Mips::RetRA16:
|
|
ExpandRetRA16(MBB, MI, Mips::JrRa16);
|
|
break;
|
|
}
|
|
|
|
MBB.erase(MI);
|
|
return true;
|
|
}
|
|
|
|
/// GetOppositeBranchOpc - Return the inverse of the specified
|
|
/// opcode, e.g. turning BEQ to BNE.
|
|
unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
|
|
assert(false && "Implement this function.");
|
|
return 0;
|
|
}
|
|
|
|
unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
|
|
return 0;
|
|
}
|
|
|
|
void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned Opc) const {
|
|
BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
|
|
}
|