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https://github.com/c64scene-ar/llvm-6502.git
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49683f3c96
The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.7 KiB
C++
77 lines
2.7 KiB
C++
//=======- NVPTXFrameLowering.cpp - NVPTX Frame Information ---*- C++ -*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the NVPTX implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXFrameLowering.h"
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#include "NVPTX.h"
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#include "NVPTXRegisterInfo.h"
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#include "NVPTXSubtarget.h"
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#include "NVPTXTargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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bool NVPTXFrameLowering::hasFP(const MachineFunction &MF) const {
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return true;
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}
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void NVPTXFrameLowering::emitPrologue(MachineFunction &MF) const {
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if (MF.getFrameInfo()->hasStackObjects()) {
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MachineBasicBlock &MBB = MF.front();
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// Insert "mov.u32 %SP, %Depot"
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MachineBasicBlock::iterator MBBI = MBB.begin();
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// This instruction really occurs before first instruction
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// in the BB, so giving it no debug location.
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DebugLoc dl = DebugLoc();
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if (tm.getSubtargetImpl()->hasGenericLdSt()) {
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// mov %SPL, %depot;
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// cvta.local %SP, %SPL;
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if (is64bit) {
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MachineInstr *MI = BuildMI(MBB, MBBI, dl,
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tm.getInstrInfo()->get(NVPTX::cvta_local_yes_64),
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NVPTX::VRFrame).addReg(NVPTX::VRFrameLocal);
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BuildMI(MBB, MI, dl,
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tm.getInstrInfo()->get(NVPTX::IMOV64rr), NVPTX::VRFrameLocal)
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.addReg(NVPTX::VRDepot);
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} else {
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MachineInstr *MI = BuildMI(MBB, MBBI, dl,
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tm.getInstrInfo()->get(NVPTX::cvta_local_yes),
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NVPTX::VRFrame).addReg(NVPTX::VRFrameLocal);
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BuildMI(MBB, MI, dl,
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tm.getInstrInfo()->get(NVPTX::IMOV32rr), NVPTX::VRFrameLocal)
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.addReg(NVPTX::VRDepot);
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}
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}
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else {
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// mov %SP, %depot;
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if (is64bit)
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BuildMI(MBB, MBBI, dl,
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tm.getInstrInfo()->get(NVPTX::IMOV64rr), NVPTX::VRFrame)
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.addReg(NVPTX::VRDepot);
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else
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BuildMI(MBB, MBBI, dl,
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tm.getInstrInfo()->get(NVPTX::IMOV32rr), NVPTX::VRFrame)
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.addReg(NVPTX::VRDepot);
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}
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}
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}
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void NVPTXFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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}
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