mirror of
https://github.com/c64scene-ar/llvm-6502.git
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af87831519
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156232 91177308-0d34-0410-b5e6-96231b3b80d8
684 lines
26 KiB
C++
684 lines
26 KiB
C++
//===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the NVPTX target.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Instructions.h"
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#include "llvm/Support/raw_ostream.h"
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#include "NVPTXISelDAGToDAG.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetIntrinsicInfo.h"
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#include "llvm/GlobalValue.h"
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#undef DEBUG_TYPE
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#define DEBUG_TYPE "nvptx-isel"
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using namespace llvm;
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static cl::opt<bool>
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UseFMADInstruction("nvptx-mad-enable",
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cl::ZeroOrMore,
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cl::desc("NVPTX Specific: Enable generating FMAD instructions"),
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cl::init(false));
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static cl::opt<int>
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FMAContractLevel("nvptx-fma-level",
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cl::ZeroOrMore,
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cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
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" 1: do it 2: do it aggressively"),
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cl::init(2));
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static cl::opt<int>
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UsePrecDivF32("nvptx-prec-divf32",
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cl::ZeroOrMore,
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cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
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" IEEE Compliant F32 div.rnd if avaiable."),
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cl::init(2));
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/// createNVPTXISelDag - This pass converts a legalized DAG into a
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/// NVPTX-specific DAG, ready for instruction scheduling.
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FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
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llvm::CodeGenOpt::Level OptLevel) {
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return new NVPTXDAGToDAGISel(TM, OptLevel);
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}
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NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
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CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(tm, OptLevel),
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Subtarget(tm.getSubtarget<NVPTXSubtarget>())
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{
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// Always do fma.f32 fpcontract if the target supports the instruction.
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// Always do fma.f64 fpcontract if the target supports the instruction.
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// Do mad.f32 is nvptx-mad-enable is specified and the target does not
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// support fma.f32.
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doFMADF32 = (OptLevel > 0) && UseFMADInstruction && !Subtarget.hasFMAF32();
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doFMAF32 = (OptLevel > 0) && Subtarget.hasFMAF32() &&
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(FMAContractLevel>=1);
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doFMAF64 = (OptLevel > 0) && Subtarget.hasFMAF64() &&
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(FMAContractLevel>=1);
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doFMAF32AGG = (OptLevel > 0) && Subtarget.hasFMAF32() &&
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(FMAContractLevel==2);
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doFMAF64AGG = (OptLevel > 0) && Subtarget.hasFMAF64() &&
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(FMAContractLevel==2);
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allowFMA = (FMAContractLevel >= 1) || UseFMADInstruction;
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UseF32FTZ = false;
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doMulWide = (OptLevel > 0);
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// Decide how to translate f32 div
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do_DIVF32_PREC = UsePrecDivF32;
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// sm less than sm_20 does not support div.rnd. Use div.full.
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if (do_DIVF32_PREC == 2 && !Subtarget.reqPTX20())
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do_DIVF32_PREC = 1;
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}
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/// Select - Select instructions not customized! Used for
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/// expanded, promoted and normal instructions.
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SDNode* NVPTXDAGToDAGISel::Select(SDNode *N) {
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if (N->isMachineOpcode())
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return NULL; // Already selected.
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SDNode *ResNode = NULL;
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switch (N->getOpcode()) {
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case ISD::LOAD:
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ResNode = SelectLoad(N);
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break;
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case ISD::STORE:
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ResNode = SelectStore(N);
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break;
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}
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if (ResNode)
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return ResNode;
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return SelectCode(N);
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}
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static unsigned int
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getCodeAddrSpace(MemSDNode *N, const NVPTXSubtarget &Subtarget)
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{
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const Value *Src = N->getSrcValue();
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if (!Src)
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return NVPTX::PTXLdStInstCode::LOCAL;
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if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) {
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switch (PT->getAddressSpace()) {
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case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
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case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
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case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
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case llvm::ADDRESS_SPACE_CONST_NOT_GEN:
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return NVPTX::PTXLdStInstCode::CONSTANT;
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case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
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case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
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case llvm::ADDRESS_SPACE_CONST:
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// If the arch supports generic address space, translate it to GLOBAL
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// for correctness.
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// If the arch does not support generic address space, then the arch
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// does not really support ADDRESS_SPACE_CONST, translate it to
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// to CONSTANT for better performance.
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if (Subtarget.hasGenericLdSt())
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return NVPTX::PTXLdStInstCode::GLOBAL;
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else
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return NVPTX::PTXLdStInstCode::CONSTANT;
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default: break;
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}
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}
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return NVPTX::PTXLdStInstCode::LOCAL;
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}
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SDNode* NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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LoadSDNode *LD = cast<LoadSDNode>(N);
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EVT LoadedVT = LD->getMemoryVT();
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SDNode *NVPTXLD= NULL;
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// do not support pre/post inc/dec
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if (LD->isIndexed())
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return NULL;
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if (!LoadedVT.isSimple())
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return NULL;
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// Address Space Setting
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unsigned int codeAddrSpace = getCodeAddrSpace(LD, Subtarget);
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// Volatile Setting
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// - .volatile is only availalble for .global and .shared
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bool isVolatile = LD->isVolatile();
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if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
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codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
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codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
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isVolatile = false;
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// Vector Setting
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MVT SimpleVT = LoadedVT.getSimpleVT();
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unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
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if (SimpleVT.isVector()) {
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unsigned num = SimpleVT.getVectorNumElements();
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if (num == 2)
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vecType = NVPTX::PTXLdStInstCode::V2;
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else if (num == 4)
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vecType = NVPTX::PTXLdStInstCode::V4;
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else
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return NULL;
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}
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// Type Setting: fromType + fromTypeWidth
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//
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// Sign : ISD::SEXTLOAD
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// Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
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// type is integer
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// Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
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MVT ScalarVT = SimpleVT.getScalarType();
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unsigned fromTypeWidth = ScalarVT.getSizeInBits();
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unsigned int fromType;
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if ((LD->getExtensionType() == ISD::SEXTLOAD))
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fromType = NVPTX::PTXLdStInstCode::Signed;
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else if (ScalarVT.isFloatingPoint())
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fromType = NVPTX::PTXLdStInstCode::Float;
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else
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fromType = NVPTX::PTXLdStInstCode::Unsigned;
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// Create the machine instruction DAG
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SDValue Chain = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SDValue Addr;
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SDValue Offset, Base;
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unsigned Opcode;
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MVT::SimpleValueType TargetVT = LD->getValueType(0).getSimpleVT().SimpleTy;
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if (SelectDirectAddr(N1, Addr)) {
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switch (TargetVT) {
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case MVT::i8: Opcode = NVPTX::LD_i8_avar; break;
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case MVT::i16: Opcode = NVPTX::LD_i16_avar; break;
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case MVT::i32: Opcode = NVPTX::LD_i32_avar; break;
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case MVT::i64: Opcode = NVPTX::LD_i64_avar; break;
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case MVT::f32: Opcode = NVPTX::LD_f32_avar; break;
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case MVT::f64: Opcode = NVPTX::LD_f64_avar; break;
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case MVT::v2i8: Opcode = NVPTX::LD_v2i8_avar; break;
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case MVT::v2i16: Opcode = NVPTX::LD_v2i16_avar; break;
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case MVT::v2i32: Opcode = NVPTX::LD_v2i32_avar; break;
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case MVT::v2i64: Opcode = NVPTX::LD_v2i64_avar; break;
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case MVT::v2f32: Opcode = NVPTX::LD_v2f32_avar; break;
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case MVT::v2f64: Opcode = NVPTX::LD_v2f64_avar; break;
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case MVT::v4i8: Opcode = NVPTX::LD_v4i8_avar; break;
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case MVT::v4i16: Opcode = NVPTX::LD_v4i16_avar; break;
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case MVT::v4i32: Opcode = NVPTX::LD_v4i32_avar; break;
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case MVT::v4f32: Opcode = NVPTX::LD_v4f32_avar; break;
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default: return NULL;
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}
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SDValue Ops[] = { getI32Imm(isVolatile),
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getI32Imm(codeAddrSpace),
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getI32Imm(vecType),
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getI32Imm(fromType),
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getI32Imm(fromTypeWidth),
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Addr, Chain };
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NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
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MVT::Other, Ops, 7);
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} else if (Subtarget.is64Bit()?
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SelectADDRsi64(N1.getNode(), N1, Base, Offset):
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SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
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switch (TargetVT) {
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case MVT::i8: Opcode = NVPTX::LD_i8_asi; break;
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case MVT::i16: Opcode = NVPTX::LD_i16_asi; break;
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case MVT::i32: Opcode = NVPTX::LD_i32_asi; break;
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case MVT::i64: Opcode = NVPTX::LD_i64_asi; break;
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case MVT::f32: Opcode = NVPTX::LD_f32_asi; break;
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case MVT::f64: Opcode = NVPTX::LD_f64_asi; break;
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case MVT::v2i8: Opcode = NVPTX::LD_v2i8_asi; break;
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case MVT::v2i16: Opcode = NVPTX::LD_v2i16_asi; break;
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case MVT::v2i32: Opcode = NVPTX::LD_v2i32_asi; break;
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case MVT::v2i64: Opcode = NVPTX::LD_v2i64_asi; break;
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case MVT::v2f32: Opcode = NVPTX::LD_v2f32_asi; break;
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case MVT::v2f64: Opcode = NVPTX::LD_v2f64_asi; break;
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case MVT::v4i8: Opcode = NVPTX::LD_v4i8_asi; break;
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case MVT::v4i16: Opcode = NVPTX::LD_v4i16_asi; break;
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case MVT::v4i32: Opcode = NVPTX::LD_v4i32_asi; break;
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case MVT::v4f32: Opcode = NVPTX::LD_v4f32_asi; break;
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default: return NULL;
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}
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SDValue Ops[] = { getI32Imm(isVolatile),
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getI32Imm(codeAddrSpace),
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getI32Imm(vecType),
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getI32Imm(fromType),
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getI32Imm(fromTypeWidth),
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Base, Offset, Chain };
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NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
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MVT::Other, Ops, 8);
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} else if (Subtarget.is64Bit()?
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SelectADDRri64(N1.getNode(), N1, Base, Offset):
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SelectADDRri(N1.getNode(), N1, Base, Offset)) {
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switch (TargetVT) {
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case MVT::i8: Opcode = NVPTX::LD_i8_ari; break;
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case MVT::i16: Opcode = NVPTX::LD_i16_ari; break;
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case MVT::i32: Opcode = NVPTX::LD_i32_ari; break;
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case MVT::i64: Opcode = NVPTX::LD_i64_ari; break;
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case MVT::f32: Opcode = NVPTX::LD_f32_ari; break;
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case MVT::f64: Opcode = NVPTX::LD_f64_ari; break;
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case MVT::v2i8: Opcode = NVPTX::LD_v2i8_ari; break;
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case MVT::v2i16: Opcode = NVPTX::LD_v2i16_ari; break;
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case MVT::v2i32: Opcode = NVPTX::LD_v2i32_ari; break;
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case MVT::v2i64: Opcode = NVPTX::LD_v2i64_ari; break;
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case MVT::v2f32: Opcode = NVPTX::LD_v2f32_ari; break;
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case MVT::v2f64: Opcode = NVPTX::LD_v2f64_ari; break;
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case MVT::v4i8: Opcode = NVPTX::LD_v4i8_ari; break;
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case MVT::v4i16: Opcode = NVPTX::LD_v4i16_ari; break;
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case MVT::v4i32: Opcode = NVPTX::LD_v4i32_ari; break;
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case MVT::v4f32: Opcode = NVPTX::LD_v4f32_ari; break;
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default: return NULL;
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}
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SDValue Ops[] = { getI32Imm(isVolatile),
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getI32Imm(codeAddrSpace),
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getI32Imm(vecType),
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getI32Imm(fromType),
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getI32Imm(fromTypeWidth),
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Base, Offset, Chain };
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NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
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MVT::Other, Ops, 8);
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}
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else {
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switch (TargetVT) {
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case MVT::i8: Opcode = NVPTX::LD_i8_areg; break;
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case MVT::i16: Opcode = NVPTX::LD_i16_areg; break;
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case MVT::i32: Opcode = NVPTX::LD_i32_areg; break;
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case MVT::i64: Opcode = NVPTX::LD_i64_areg; break;
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case MVT::f32: Opcode = NVPTX::LD_f32_areg; break;
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case MVT::f64: Opcode = NVPTX::LD_f64_areg; break;
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case MVT::v2i8: Opcode = NVPTX::LD_v2i8_areg; break;
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case MVT::v2i16: Opcode = NVPTX::LD_v2i16_areg; break;
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case MVT::v2i32: Opcode = NVPTX::LD_v2i32_areg; break;
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case MVT::v2i64: Opcode = NVPTX::LD_v2i64_areg; break;
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case MVT::v2f32: Opcode = NVPTX::LD_v2f32_areg; break;
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case MVT::v2f64: Opcode = NVPTX::LD_v2f64_areg; break;
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case MVT::v4i8: Opcode = NVPTX::LD_v4i8_areg; break;
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case MVT::v4i16: Opcode = NVPTX::LD_v4i16_areg; break;
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case MVT::v4i32: Opcode = NVPTX::LD_v4i32_areg; break;
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case MVT::v4f32: Opcode = NVPTX::LD_v4f32_areg; break;
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default: return NULL;
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}
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SDValue Ops[] = { getI32Imm(isVolatile),
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getI32Imm(codeAddrSpace),
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getI32Imm(vecType),
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getI32Imm(fromType),
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getI32Imm(fromTypeWidth),
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N1, Chain };
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NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
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MVT::Other, Ops, 7);
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}
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if (NVPTXLD != NULL) {
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MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
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MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
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cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
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}
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return NVPTXLD;
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}
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SDNode* NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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StoreSDNode *ST = cast<StoreSDNode>(N);
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EVT StoreVT = ST->getMemoryVT();
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SDNode *NVPTXST = NULL;
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// do not support pre/post inc/dec
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if (ST->isIndexed())
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return NULL;
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if (!StoreVT.isSimple())
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return NULL;
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// Address Space Setting
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unsigned int codeAddrSpace = getCodeAddrSpace(ST, Subtarget);
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// Volatile Setting
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// - .volatile is only availalble for .global and .shared
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bool isVolatile = ST->isVolatile();
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if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
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codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
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codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
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isVolatile = false;
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// Vector Setting
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MVT SimpleVT = StoreVT.getSimpleVT();
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unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
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if (SimpleVT.isVector()) {
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unsigned num = SimpleVT.getVectorNumElements();
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if (num == 2)
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vecType = NVPTX::PTXLdStInstCode::V2;
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else if (num == 4)
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vecType = NVPTX::PTXLdStInstCode::V4;
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else
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return NULL;
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}
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// Type Setting: toType + toTypeWidth
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// - for integer type, always use 'u'
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//
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MVT ScalarVT = SimpleVT.getScalarType();
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unsigned toTypeWidth = ScalarVT.getSizeInBits();
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unsigned int toType;
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if (ScalarVT.isFloatingPoint())
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toType = NVPTX::PTXLdStInstCode::Float;
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else
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toType = NVPTX::PTXLdStInstCode::Unsigned;
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// Create the machine instruction DAG
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SDValue Chain = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SDValue N2 = N->getOperand(2);
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SDValue Addr;
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SDValue Offset, Base;
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unsigned Opcode;
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MVT::SimpleValueType SourceVT =
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N1.getNode()->getValueType(0).getSimpleVT().SimpleTy;
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if (SelectDirectAddr(N2, Addr)) {
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switch (SourceVT) {
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case MVT::i8: Opcode = NVPTX::ST_i8_avar; break;
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case MVT::i16: Opcode = NVPTX::ST_i16_avar; break;
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case MVT::i32: Opcode = NVPTX::ST_i32_avar; break;
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case MVT::i64: Opcode = NVPTX::ST_i64_avar; break;
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case MVT::f32: Opcode = NVPTX::ST_f32_avar; break;
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case MVT::f64: Opcode = NVPTX::ST_f64_avar; break;
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case MVT::v2i8: Opcode = NVPTX::ST_v2i8_avar; break;
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case MVT::v2i16: Opcode = NVPTX::ST_v2i16_avar; break;
|
|
case MVT::v2i32: Opcode = NVPTX::ST_v2i32_avar; break;
|
|
case MVT::v2i64: Opcode = NVPTX::ST_v2i64_avar; break;
|
|
case MVT::v2f32: Opcode = NVPTX::ST_v2f32_avar; break;
|
|
case MVT::v2f64: Opcode = NVPTX::ST_v2f64_avar; break;
|
|
case MVT::v4i8: Opcode = NVPTX::ST_v4i8_avar; break;
|
|
case MVT::v4i16: Opcode = NVPTX::ST_v4i16_avar; break;
|
|
case MVT::v4i32: Opcode = NVPTX::ST_v4i32_avar; break;
|
|
case MVT::v4f32: Opcode = NVPTX::ST_v4f32_avar; break;
|
|
default: return NULL;
|
|
}
|
|
SDValue Ops[] = { N1,
|
|
getI32Imm(isVolatile),
|
|
getI32Imm(codeAddrSpace),
|
|
getI32Imm(vecType),
|
|
getI32Imm(toType),
|
|
getI32Imm(toTypeWidth),
|
|
Addr, Chain };
|
|
NVPTXST = CurDAG->getMachineNode(Opcode, dl,
|
|
MVT::Other, Ops, 8);
|
|
} else if (Subtarget.is64Bit()?
|
|
SelectADDRsi64(N2.getNode(), N2, Base, Offset):
|
|
SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
|
|
switch (SourceVT) {
|
|
case MVT::i8: Opcode = NVPTX::ST_i8_asi; break;
|
|
case MVT::i16: Opcode = NVPTX::ST_i16_asi; break;
|
|
case MVT::i32: Opcode = NVPTX::ST_i32_asi; break;
|
|
case MVT::i64: Opcode = NVPTX::ST_i64_asi; break;
|
|
case MVT::f32: Opcode = NVPTX::ST_f32_asi; break;
|
|
case MVT::f64: Opcode = NVPTX::ST_f64_asi; break;
|
|
case MVT::v2i8: Opcode = NVPTX::ST_v2i8_asi; break;
|
|
case MVT::v2i16: Opcode = NVPTX::ST_v2i16_asi; break;
|
|
case MVT::v2i32: Opcode = NVPTX::ST_v2i32_asi; break;
|
|
case MVT::v2i64: Opcode = NVPTX::ST_v2i64_asi; break;
|
|
case MVT::v2f32: Opcode = NVPTX::ST_v2f32_asi; break;
|
|
case MVT::v2f64: Opcode = NVPTX::ST_v2f64_asi; break;
|
|
case MVT::v4i8: Opcode = NVPTX::ST_v4i8_asi; break;
|
|
case MVT::v4i16: Opcode = NVPTX::ST_v4i16_asi; break;
|
|
case MVT::v4i32: Opcode = NVPTX::ST_v4i32_asi; break;
|
|
case MVT::v4f32: Opcode = NVPTX::ST_v4f32_asi; break;
|
|
default: return NULL;
|
|
}
|
|
SDValue Ops[] = { N1,
|
|
getI32Imm(isVolatile),
|
|
getI32Imm(codeAddrSpace),
|
|
getI32Imm(vecType),
|
|
getI32Imm(toType),
|
|
getI32Imm(toTypeWidth),
|
|
Base, Offset, Chain };
|
|
NVPTXST = CurDAG->getMachineNode(Opcode, dl,
|
|
MVT::Other, Ops, 9);
|
|
} else if (Subtarget.is64Bit()?
|
|
SelectADDRri64(N2.getNode(), N2, Base, Offset):
|
|
SelectADDRri(N2.getNode(), N2, Base, Offset)) {
|
|
switch (SourceVT) {
|
|
case MVT::i8: Opcode = NVPTX::ST_i8_ari; break;
|
|
case MVT::i16: Opcode = NVPTX::ST_i16_ari; break;
|
|
case MVT::i32: Opcode = NVPTX::ST_i32_ari; break;
|
|
case MVT::i64: Opcode = NVPTX::ST_i64_ari; break;
|
|
case MVT::f32: Opcode = NVPTX::ST_f32_ari; break;
|
|
case MVT::f64: Opcode = NVPTX::ST_f64_ari; break;
|
|
case MVT::v2i8: Opcode = NVPTX::ST_v2i8_ari; break;
|
|
case MVT::v2i16: Opcode = NVPTX::ST_v2i16_ari; break;
|
|
case MVT::v2i32: Opcode = NVPTX::ST_v2i32_ari; break;
|
|
case MVT::v2i64: Opcode = NVPTX::ST_v2i64_ari; break;
|
|
case MVT::v2f32: Opcode = NVPTX::ST_v2f32_ari; break;
|
|
case MVT::v2f64: Opcode = NVPTX::ST_v2f64_ari; break;
|
|
case MVT::v4i8: Opcode = NVPTX::ST_v4i8_ari; break;
|
|
case MVT::v4i16: Opcode = NVPTX::ST_v4i16_ari; break;
|
|
case MVT::v4i32: Opcode = NVPTX::ST_v4i32_ari; break;
|
|
case MVT::v4f32: Opcode = NVPTX::ST_v4f32_ari; break;
|
|
default: return NULL;
|
|
}
|
|
SDValue Ops[] = { N1,
|
|
getI32Imm(isVolatile),
|
|
getI32Imm(codeAddrSpace),
|
|
getI32Imm(vecType),
|
|
getI32Imm(toType),
|
|
getI32Imm(toTypeWidth),
|
|
Base, Offset, Chain };
|
|
NVPTXST = CurDAG->getMachineNode(Opcode, dl,
|
|
MVT::Other, Ops, 9);
|
|
} else {
|
|
switch (SourceVT) {
|
|
case MVT::i8: Opcode = NVPTX::ST_i8_areg; break;
|
|
case MVT::i16: Opcode = NVPTX::ST_i16_areg; break;
|
|
case MVT::i32: Opcode = NVPTX::ST_i32_areg; break;
|
|
case MVT::i64: Opcode = NVPTX::ST_i64_areg; break;
|
|
case MVT::f32: Opcode = NVPTX::ST_f32_areg; break;
|
|
case MVT::f64: Opcode = NVPTX::ST_f64_areg; break;
|
|
case MVT::v2i8: Opcode = NVPTX::ST_v2i8_areg; break;
|
|
case MVT::v2i16: Opcode = NVPTX::ST_v2i16_areg; break;
|
|
case MVT::v2i32: Opcode = NVPTX::ST_v2i32_areg; break;
|
|
case MVT::v2i64: Opcode = NVPTX::ST_v2i64_areg; break;
|
|
case MVT::v2f32: Opcode = NVPTX::ST_v2f32_areg; break;
|
|
case MVT::v2f64: Opcode = NVPTX::ST_v2f64_areg; break;
|
|
case MVT::v4i8: Opcode = NVPTX::ST_v4i8_areg; break;
|
|
case MVT::v4i16: Opcode = NVPTX::ST_v4i16_areg; break;
|
|
case MVT::v4i32: Opcode = NVPTX::ST_v4i32_areg; break;
|
|
case MVT::v4f32: Opcode = NVPTX::ST_v4f32_areg; break;
|
|
default: return NULL;
|
|
}
|
|
SDValue Ops[] = { N1,
|
|
getI32Imm(isVolatile),
|
|
getI32Imm(codeAddrSpace),
|
|
getI32Imm(vecType),
|
|
getI32Imm(toType),
|
|
getI32Imm(toTypeWidth),
|
|
N2, Chain };
|
|
NVPTXST = CurDAG->getMachineNode(Opcode, dl,
|
|
MVT::Other, Ops, 8);
|
|
}
|
|
|
|
if (NVPTXST != NULL) {
|
|
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
|
|
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
|
|
cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
|
|
}
|
|
|
|
return NVPTXST;
|
|
}
|
|
|
|
// SelectDirectAddr - Match a direct address for DAG.
|
|
// A direct address could be a globaladdress or externalsymbol.
|
|
bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
|
|
// Return true if TGA or ES.
|
|
if (N.getOpcode() == ISD::TargetGlobalAddress
|
|
|| N.getOpcode() == ISD::TargetExternalSymbol) {
|
|
Address = N;
|
|
return true;
|
|
}
|
|
if (N.getOpcode() == NVPTXISD::Wrapper) {
|
|
Address = N.getOperand(0);
|
|
return true;
|
|
}
|
|
if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
|
|
unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
|
|
if (IID == Intrinsic::nvvm_ptr_gen_to_param)
|
|
if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
|
|
return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
|
|
}
|
|
return false;
|
|
}
|
|
|
|
// symbol+offset
|
|
bool NVPTXDAGToDAGISel::SelectADDRsi_imp(SDNode *OpNode, SDValue Addr,
|
|
SDValue &Base, SDValue &Offset,
|
|
MVT mvt) {
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
|
|
SDValue base=Addr.getOperand(0);
|
|
if (SelectDirectAddr(base, Base)) {
|
|
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
// symbol+offset
|
|
bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
|
|
SDValue &Base, SDValue &Offset) {
|
|
return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
|
|
}
|
|
|
|
// symbol+offset
|
|
bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
|
|
SDValue &Base, SDValue &Offset) {
|
|
return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
|
|
}
|
|
|
|
// register+offset
|
|
bool NVPTXDAGToDAGISel::SelectADDRri_imp(SDNode *OpNode, SDValue Addr,
|
|
SDValue &Base, SDValue &Offset,
|
|
MVT mvt) {
|
|
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
|
|
Offset = CurDAG->getTargetConstant(0, mvt);
|
|
return true;
|
|
}
|
|
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
|
|
Addr.getOpcode() == ISD::TargetGlobalAddress)
|
|
return false; // direct calls.
|
|
|
|
if (Addr.getOpcode() == ISD::ADD) {
|
|
if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
|
|
return false;
|
|
}
|
|
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
|
|
if (FrameIndexSDNode *FIN =
|
|
dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
|
|
// Constant offset from frame ref.
|
|
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
|
|
else
|
|
Base = Addr.getOperand(0);
|
|
Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
// register+offset
|
|
bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
|
|
SDValue &Base, SDValue &Offset) {
|
|
return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
|
|
}
|
|
|
|
// register+offset
|
|
bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
|
|
SDValue &Base, SDValue &Offset) {
|
|
return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
|
|
}
|
|
|
|
bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
|
|
unsigned int spN) const {
|
|
const Value *Src = NULL;
|
|
// Even though MemIntrinsicSDNode is a subclas of MemSDNode,
|
|
// the classof() for MemSDNode does not include MemIntrinsicSDNode
|
|
// (See SelectionDAGNodes.h). So we need to check for both.
|
|
if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
|
|
Src = mN->getSrcValue();
|
|
}
|
|
else if (MemSDNode *mN = dyn_cast<MemIntrinsicSDNode>(N)) {
|
|
Src = mN->getSrcValue();
|
|
}
|
|
if (!Src)
|
|
return false;
|
|
if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
|
|
return (PT->getAddressSpace() == spN);
|
|
return false;
|
|
}
|
|
|
|
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
|
|
/// inline asm expressions.
|
|
bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
|
|
char ConstraintCode,
|
|
std::vector<SDValue> &OutOps) {
|
|
SDValue Op0, Op1;
|
|
switch (ConstraintCode) {
|
|
default: return true;
|
|
case 'm': // memory
|
|
if (SelectDirectAddr(Op, Op0)) {
|
|
OutOps.push_back(Op0);
|
|
OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
|
|
return false;
|
|
}
|
|
if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
|
|
OutOps.push_back(Op0);
|
|
OutOps.push_back(Op1);
|
|
return false;
|
|
}
|
|
break;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
// Return true if N is a undef or a constant.
|
|
// If N was undef, return a (i8imm 0) in Retval
|
|
// If N was imm, convert it to i8imm and return in Retval
|
|
// Note: The convert to i8imm is required, otherwise the
|
|
// pattern matcher inserts a bunch of IMOVi8rr to convert
|
|
// the imm to i8imm, and this causes instruction selection
|
|
// to fail.
|
|
bool NVPTXDAGToDAGISel::UndefOrImm(SDValue Op, SDValue N,
|
|
SDValue &Retval) {
|
|
if (!(N.getOpcode() == ISD::UNDEF) &&
|
|
!(N.getOpcode() == ISD::Constant))
|
|
return false;
|
|
|
|
if (N.getOpcode() == ISD::UNDEF)
|
|
Retval = CurDAG->getTargetConstant(0, MVT::i8);
|
|
else {
|
|
ConstantSDNode *cn = cast<ConstantSDNode>(N.getNode());
|
|
unsigned retval = cn->getZExtValue();
|
|
Retval = CurDAG->getTargetConstant(retval, MVT::i8);
|
|
}
|
|
return true;
|
|
}
|