mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
fe2b8b1960
Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221534 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.3 KiB
LLVM
49 lines
1.3 KiB
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK
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; RUN: llc -march=mips64el < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK64
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; CHECK-LABEL: mul5_32:
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; CHECK: sll $[[R0:[0-9]+]], $4, 2
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; CHECK: addu ${{[0-9]+}}, $[[R0]], $4
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define i32 @mul5_32(i32 signext %a) {
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entry:
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%mul = mul nsw i32 %a, 5
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ret i32 %mul
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}
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; CHECK-LABEL: mul27_32:
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; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
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; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
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; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5
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; CHECK: subu ${{[0-9]+}}, $[[R2]], $[[R1]]
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define i32 @mul27_32(i32 signext %a) {
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entry:
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%mul = mul nsw i32 %a, 27
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ret i32 %mul
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}
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; CHECK-LABEL: muln2147483643_32:
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; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
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; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
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; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31
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; CHECK: addu ${{[0-9]+}}, $[[R2]], $[[R1]]
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define i32 @muln2147483643_32(i32 signext %a) {
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entry:
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%mul = mul nsw i32 %a, -2147483643
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ret i32 %mul
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}
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; CHECK64-LABEL: muln9223372036854775805_64:
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; CHECK64-DAG: dsll $[[R0:[0-9]+]], $4, 1
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; CHECK64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], $4
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; CHECK64-DAG: dsll $[[R2:[0-9]+]], $4, 63
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; CHECK64: daddu ${{[0-9]+}}, $[[R2]], $[[R1]]
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define i64 @muln9223372036854775805_64(i64 signext %a) {
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entry:
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%mul = mul nsw i64 %a, -9223372036854775805
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ret i64 %mul
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}
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