mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1ec5bd31fe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122147 91177308-0d34-0410-b5e6-96231b3b80d8
471 lines
16 KiB
C++
471 lines
16 KiB
C++
//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMFixupKinds.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCMachObjectWriter.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/Object/MachOFormat.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetAsmBackend.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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namespace {
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class ARMMachObjectWriter : public MCMachObjectTargetWriter {
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public:
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ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
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uint32_t CPUSubtype)
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: MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
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/*UseAggressiveSymbolFolding=*/true) {}
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};
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class ARMELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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ARMELFObjectWriter(Triple::OSType OSType)
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: MCELFObjectTargetWriter(/*Is64Bit*/ false, OSType, ELF::EM_ARM,
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/*HasRelocationAddend*/ false) {}
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};
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class ARMAsmBackend : public TargetAsmBackend {
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bool isThumbMode; // Currently emitting Thumb code.
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public:
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ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {}
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unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = {
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// This table *must* be in the order that the fixup_* kinds are defined in
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// ARMFixupKinds.h.
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//
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// Name Offset (bits) Size (bits) Flags
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{ "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{ "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
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MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
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{ "fixup_arm_branch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_blx", 7, 21, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_arm_movt_hi16", 0, 16, 0 },
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{ "fixup_arm_movw_lo16", 0, 16, 0 },
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};
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if (Kind < FirstTargetFixupKind)
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return TargetAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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bool MayNeedRelaxation(const MCInst &Inst) const;
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void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
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bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
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void HandleAssemblerFlag(MCAssemblerFlag Flag) {
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switch (Flag) {
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default: break;
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case MCAF_Code16:
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setIsThumb(true);
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break;
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case MCAF_Code32:
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setIsThumb(false);
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break;
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}
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}
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unsigned getPointerSize() const { return 4; }
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bool isThumb() const { return isThumbMode; }
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void setIsThumb(bool it) { isThumbMode = it; }
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};
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} // end anonymous namespace
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bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
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// FIXME: Thumb targets, different move constant targets..
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return false;
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}
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void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
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assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
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return;
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}
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bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
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if (isThumb()) {
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// FIXME: 0xbf00 is the ARMv7 value. For v6 and before, we'll need to
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// use 0x46c0 (which is a 'mov r8, r8' insn).
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uint64_t NumNops = Count / 2;
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for (uint64_t i = 0; i != NumNops; ++i)
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OW->Write16(0xbf00);
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if (Count & 1)
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OW->Write8(0);
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return true;
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}
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// ARM mode
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uint64_t NumNops = Count / 4;
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for (uint64_t i = 0; i != NumNops; ++i)
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OW->Write32(0xe1a00000);
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switch (Count % 4) {
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default: break; // No leftover bytes to write
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case 1: OW->Write8(0); break;
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case 2: OW->Write16(0); break;
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case 3: OW->Write16(0); OW->Write8(0xa0); break;
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}
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return true;
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}
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static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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return Value;
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case ARM::fixup_arm_movt_hi16:
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case ARM::fixup_arm_movw_lo16: {
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unsigned Hi4 = (Value & 0xF000) >> 12;
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unsigned Lo12 = Value & 0x0FFF;
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// inst{19-16} = Hi4;
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// inst{11-0} = Lo12;
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Value = (Hi4 << 16) | (Lo12);
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return Value;
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}
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case ARM::fixup_arm_ldst_pcrel_12:
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// ARM PC-relative values are offset by 8.
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Value -= 4;
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// FALLTHROUGH
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case ARM::fixup_t2_ldst_pcrel_12: {
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// Offset by 4, adjusted by two due to the half-word ordering of thumb.
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Value -= 4;
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bool isAdd = true;
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if ((int64_t)Value < 0) {
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Value = -Value;
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isAdd = false;
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}
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assert ((Value < 4096) && "Out of range pc-relative fixup value!");
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Value |= isAdd << 23;
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// Same addressing mode as fixup_arm_pcrel_10,
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// but with 16-bit halfwords swapped.
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if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
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uint64_t swapped = (Value & 0xFFFF0000) >> 16;
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swapped |= (Value & 0x0000FFFF) << 16;
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return swapped;
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}
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return Value;
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}
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case ARM::fixup_thumb_adr_pcrel_10:
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return ((Value - 4) >> 2) & 0xff;
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case ARM::fixup_arm_adr_pcrel_12: {
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// ARM PC-relative values are offset by 8.
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Value -= 8;
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unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
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if ((int64_t)Value < 0) {
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Value = -Value;
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opc = 2; // 0b0010
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}
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assert(ARM_AM::getSOImmVal(Value) != -1 &&
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"Out of range pc-relative fixup value!");
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// Encode the immediate and shift the opcode into place.
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return ARM_AM::getSOImmVal(Value) | (opc << 21);
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}
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case ARM::fixup_t2_adr_pcrel_12: {
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Value -= 4;
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unsigned opc = 0;
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if ((int64_t)Value < 0) {
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Value = -Value;
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opc = 5;
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}
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uint32_t out = (opc << 21);
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out |= (Value & 0x800) << 14;
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out |= (Value & 0x700) << 4;
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out |= (Value & 0x0FF);
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uint64_t swapped = (out & 0xFFFF0000) >> 16;
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swapped |= (out & 0x0000FFFF) << 16;
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return swapped;
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}
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case ARM::fixup_arm_branch:
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// These values don't encode the low two bits since they're always zero.
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// Offset by 8 just as above.
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return 0xffffff & ((Value - 8) >> 2);
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case ARM::fixup_t2_uncondbranch: {
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Value = Value - 4;
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Value >>= 1; // Low bit is not encoded.
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uint32_t out = 0;
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bool I = Value & 0x800000;
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bool J1 = Value & 0x400000;
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bool J2 = Value & 0x200000;
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J1 ^= I;
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J2 ^= I;
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out |= I << 26; // S bit
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out |= !J1 << 13; // J1 bit
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out |= !J2 << 11; // J2 bit
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out |= (Value & 0x1FF800) << 5; // imm6 field
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out |= (Value & 0x0007FF); // imm11 field
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uint64_t swapped = (out & 0xFFFF0000) >> 16;
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swapped |= (out & 0x0000FFFF) << 16;
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return swapped;
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}
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case ARM::fixup_t2_condbranch: {
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Value = Value - 4;
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Value >>= 1; // Low bit is not encoded.
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uint64_t out = 0;
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out |= (Value & 0x80000) << 7; // S bit
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out |= (Value & 0x40000) >> 7; // J2 bit
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out |= (Value & 0x20000) >> 4; // J1 bit
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out |= (Value & 0x1F800) << 5; // imm6 field
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out |= (Value & 0x007FF); // imm11 field
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uint32_t swapped = (out & 0xFFFF0000) >> 16;
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swapped |= (out & 0x0000FFFF) << 16;
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return swapped;
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}
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case ARM::fixup_arm_thumb_bl: {
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// The value doesn't encode the low bit (always zero) and is offset by
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// four. The value is encoded into disjoint bit positions in the destination
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// opcode. x = unchanged, I = immediate value bit, S = sign extension bit
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//
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// BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
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//
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// Note that the halfwords are stored high first, low second; so we need
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// to transpose the fixup value here to map properly.
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unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
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uint32_t Binary = 0;
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Value = 0x3fffff & ((Value - 4) >> 1);
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Binary = (Value & 0x7ff) << 16; // Low imm11 value.
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Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
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Binary |= isNeg << 10; // Sign bit.
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return Binary;
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}
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case ARM::fixup_arm_thumb_blx: {
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// The value doesn't encode the low two bits (always zero) and is offset by
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// four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
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// positions in the destination opcode. x = unchanged, I = immediate value
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// bit, S = sign extension bit, 0 = zero.
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//
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// BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
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//
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// Note that the halfwords are stored high first, low second; so we need
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// to transpose the fixup value here to map properly.
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unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
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uint32_t Binary = 0;
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Value = 0xfffff & ((Value - 2) >> 2);
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Binary = (Value & 0x3ff) << 17; // Low imm10L value.
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Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
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Binary |= isNeg << 10; // Sign bit.
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return Binary;
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}
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case ARM::fixup_arm_thumb_cp:
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// Offset by 4, and don't encode the low two bits. Two bytes of that
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// 'off by 4' is implicitly handled by the half-word ordering of the
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// Thumb encoding, so we only need to adjust by 2 here.
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return ((Value - 2) >> 2) & 0xff;
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case ARM::fixup_arm_thumb_cb: {
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// Offset by 4 and don't encode the lower bit, which is always 0.
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uint32_t Binary = (Value - 4) >> 1;
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return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
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}
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case ARM::fixup_arm_thumb_br:
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// Offset by 4 and don't encode the lower bit, which is always 0.
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return ((Value - 4) >> 1) & 0x7ff;
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case ARM::fixup_arm_thumb_bcc:
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// Offset by 4 and don't encode the lower bit, which is always 0.
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return ((Value - 4) >> 1) & 0xff;
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case ARM::fixup_arm_pcrel_10:
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Value = Value - 4; // ARM fixups offset by an additional word and don't
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// need to adjust for the half-word ordering.
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// Fall through.
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case ARM::fixup_t2_pcrel_10: {
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// Offset by 4, adjusted by two due to the half-word ordering of thumb.
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Value = Value - 4;
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bool isAdd = true;
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if ((int64_t)Value < 0) {
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Value = -Value;
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isAdd = false;
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}
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// These values don't encode the low two bits since they're always zero.
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Value >>= 2;
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assert ((Value < 256) && "Out of range pc-relative fixup value!");
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Value |= isAdd << 23;
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// Same addressing mode as fixup_arm_pcrel_10,
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// but with 16-bit halfwords swapped.
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if (Kind == ARM::fixup_t2_pcrel_10) {
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uint32_t swapped = (Value & 0xFFFF0000) >> 16;
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swapped |= (Value & 0x0000FFFF) << 16;
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return swapped;
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}
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return Value;
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}
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}
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}
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namespace {
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// FIXME: This should be in a separate file.
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// ELF is an ELF of course...
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class ELFARMAsmBackend : public ARMAsmBackend {
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public:
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Triple::OSType OSType;
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ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
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: ARMAsmBackend(T), OSType(_OSType) { }
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void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value) const;
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createELFObjectWriter(new ARMELFObjectWriter(OSType), OS,
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/*IsLittleEndian*/ true);
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}
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};
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// FIXME: Raise this to share code between Darwin and ELF.
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void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
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unsigned DataSize, uint64_t Value) const {
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unsigned NumBytes = 4; // FIXME: 2 for Thumb
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Value = adjustFixupValue(Fixup.getKind(), Value);
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if (!Value) return; // Doesn't change encoding.
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unsigned Offset = Fixup.getOffset();
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assert(Offset % NumBytes == 0 && "Offset mod NumBytes is nonzero!");
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// For each byte of the fragment that the fixup touches, mask in the bits from
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// the fixup value. The Value has been "split up" into the appropriate
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// bitfields above.
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for (unsigned i = 0; i != NumBytes; ++i)
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Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
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}
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// FIXME: This should be in a separate file.
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class DarwinARMAsmBackend : public ARMAsmBackend {
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public:
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DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) { }
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void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value) const;
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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// FIXME: Subtarget info should be derived. Force v7 for now.
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return createMachObjectWriter(new ARMMachObjectWriter(
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/*Is64Bit=*/false,
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object::mach::CTM_ARM,
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object::mach::CSARM_V7),
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OS,
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/*IsLittleEndian=*/true);
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}
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virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
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return false;
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}
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};
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/// getFixupKindNumBytes - The number of bytes the fixup may change.
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static unsigned getFixupKindNumBytes(unsigned Kind) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_1:
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case ARM::fixup_arm_thumb_bcc:
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case ARM::fixup_arm_thumb_cp:
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case ARM::fixup_thumb_adr_pcrel_10:
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return 1;
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case FK_Data_2:
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case ARM::fixup_arm_thumb_br:
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case ARM::fixup_arm_thumb_cb:
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return 2;
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case ARM::fixup_arm_ldst_pcrel_12:
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case ARM::fixup_arm_pcrel_10:
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case ARM::fixup_arm_adr_pcrel_12:
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case ARM::fixup_arm_branch:
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return 3;
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case FK_Data_4:
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case ARM::fixup_t2_ldst_pcrel_12:
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case ARM::fixup_t2_condbranch:
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case ARM::fixup_t2_uncondbranch:
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case ARM::fixup_t2_pcrel_10:
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case ARM::fixup_t2_adr_pcrel_12:
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case ARM::fixup_arm_thumb_bl:
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case ARM::fixup_arm_thumb_blx:
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return 4;
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}
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}
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void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
|
|
unsigned DataSize, uint64_t Value) const {
|
|
unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
|
|
Value = adjustFixupValue(Fixup.getKind(), Value);
|
|
if (!Value) return; // Doesn't change encoding.
|
|
|
|
unsigned Offset = Fixup.getOffset();
|
|
assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
|
|
|
|
// For each byte of the fragment that the fixup touches, mask in the
|
|
// bits from the fixup value.
|
|
for (unsigned i = 0; i != NumBytes; ++i)
|
|
Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
|
|
}
|
|
|
|
} // end anonymous namespace
|
|
|
|
TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
|
|
const std::string &TT) {
|
|
switch (Triple(TT).getOS()) {
|
|
case Triple::Darwin:
|
|
return new DarwinARMAsmBackend(T);
|
|
case Triple::MinGW32:
|
|
case Triple::Cygwin:
|
|
case Triple::Win32:
|
|
assert(0 && "Windows not supported on ARM");
|
|
default:
|
|
return new ELFARMAsmBackend(T, Triple(TT).getOS());
|
|
}
|
|
}
|