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subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
2.3 KiB
TableGen
61 lines
2.3 KiB
TableGen
//===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Functional Units
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def LUNIT : FuncUnit;
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def LSUNIT : FuncUnit;
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def MUNIT : FuncUnit;
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def SUNIT : FuncUnit;
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// Itinerary classes
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def ALU32 : InstrItinClass;
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def ALU64 : InstrItinClass;
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def CR : InstrItinClass;
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def J : InstrItinClass;
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def JR : InstrItinClass;
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def LD : InstrItinClass;
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def M : InstrItinClass;
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def ST : InstrItinClass;
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def S : InstrItinClass;
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def SYS : InstrItinClass;
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def MARKER : InstrItinClass;
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def PSEUDO : InstrItinClass;
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def HexagonItineraries :
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ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [
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InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
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InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,
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InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,
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InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,
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InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,
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InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,
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InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,
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InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,
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InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,
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InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>,
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InstrItinData<MARKER , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
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InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>
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]>;
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def HexagonModel : SchedMachineModel {
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// Max issue per cycle == bundle width.
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let IssueWidth = 4;
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let Itineraries = HexagonItineraries;
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}
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//===----------------------------------------------------------------------===//
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// V4 Machine Info +
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//===----------------------------------------------------------------------===//
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include "HexagonScheduleV4.td"
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//===----------------------------------------------------------------------===//
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// V4 Machine Info -
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//===----------------------------------------------------------------------===//
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