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https://github.com/c64scene-ar/llvm-6502.git
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f99998a2b0
Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
134 lines
4.6 KiB
C++
134 lines
4.6 KiB
C++
//===-- Mips16FrameLowering.cpp - Mips16 Frame Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips16 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips16FrameLowering.h"
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#include "MipsInstrInfo.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/DataLayout.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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void Mips16FrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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uint64_t StackSize = MFI->getStackSize();
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->adjustsStack()) return;
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// Adjust stack.
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if (isInt<16>(-StackSize))
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BuildMI(MBB, MBBI, dl, TII.get(Mips::SaveRaF16)).addImm(StackSize);
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if (hasFP(MF))
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BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
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.addReg(Mips::SP);
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}
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void Mips16FrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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uint64_t StackSize = MFI->getStackSize();
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if (!StackSize)
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return;
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if (hasFP(MF))
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BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
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.addReg(Mips::S0);
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// Adjust stack.
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if (isInt<16>(StackSize))
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// assumes stacksize multiple of 8
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BuildMI(MBB, MBBI, dl, TII.get(Mips::RestoreRaF16)).addImm(StackSize);
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}
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bool Mips16FrameLowering::
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spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineFunction *MF = MBB.getParent();
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MachineBasicBlock *EntryBlock = MF->begin();
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//
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// Registers RA, S0,S1 are the callee saved registers and they
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// will be saved with the "save" instruction
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// during emitPrologue
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//
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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// Add the callee-saved register as live-in. Do not add if the register is
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// RA and return address is taken, because it has already been added in
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// method MipsTargetLowering::LowerRETURNADDR.
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// It's killed at the spill, unless the register is RA and return address
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// is taken.
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unsigned Reg = CSI[i].getReg();
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bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
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&& MF->getFrameInfo()->isReturnAddressTaken();
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if (!IsRAAndRetAddrIsTaken)
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EntryBlock->addLiveIn(Reg);
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}
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return true;
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}
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bool Mips16FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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//
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// Registers RA,S0,S1 are the callee saved registers and they will be restored
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// with the restore instruction during emitEpilogue.
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// We need to override this virtual function, otherwise llvm will try and
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// restore the registers on it's on from the stack.
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//
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return true;
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}
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bool
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Mips16FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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// FIXME: implement.
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return true;
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}
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void Mips16FrameLowering::
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processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const {
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MF.getRegInfo().setPhysRegUsed(Mips::RA);
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MF.getRegInfo().setPhysRegUsed(Mips::S0);
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MF.getRegInfo().setPhysRegUsed(Mips::S1);
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}
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const MipsFrameLowering *
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llvm::createMips16FrameLowering(const MipsSubtarget &ST) {
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return new Mips16FrameLowering(ST);
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}
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