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https://github.com/c64scene-ar/llvm-6502.git
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f99998a2b0
Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.5 KiB
C++
77 lines
2.5 KiB
C++
//===-- MipsMachineFunctionInfo.h - Private data used for Mips ----*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Mips specific subclass of MachineFunctionInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPS_MACHINE_FUNCTION_INFO_H
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#define MIPS_MACHINE_FUNCTION_INFO_H
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#include "MipsSubtarget.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include <utility>
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namespace llvm {
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/// MipsFunctionInfo - This class is derived from MachineFunction private
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/// Mips target-specific information for each MachineFunction.
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class MipsFunctionInfo : public MachineFunctionInfo {
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virtual void anchor();
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MachineFunction& MF;
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/// SRetReturnReg - Some subtargets require that sret lowering includes
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/// returning the value of the returned struct in a register. This field
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/// holds the virtual register into which the sret argument is passed.
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unsigned SRetReturnReg;
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/// GlobalBaseReg - keeps track of the virtual register initialized for
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/// use as the global base register. This is used for PIC in some PIC
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/// relocation models.
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unsigned GlobalBaseReg;
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/// Mips16SPAliasReg - keeps track of the virtual register initialized for
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/// use as an alias for SP for use in load/store of halfword/byte from/to
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/// the stack
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unsigned Mips16SPAliasReg;
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/// VarArgsFrameIndex - FrameIndex for start of varargs area.
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int VarArgsFrameIndex;
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bool EmitNOAT;
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public:
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MipsFunctionInfo(MachineFunction& MF)
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: MF(MF), SRetReturnReg(0), GlobalBaseReg(0), Mips16SPAliasReg(0),
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VarArgsFrameIndex(0), EmitNOAT(false)
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{}
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unsigned getSRetReturnReg() const { return SRetReturnReg; }
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void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
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bool globalBaseRegSet() const;
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unsigned getGlobalBaseReg();
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bool mips16SPAliasRegSet() const;
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unsigned getMips16SPAliasReg();
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int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
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void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
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bool getEmitNOAT() const { return EmitNOAT; }
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void setEmitNOAT() { EmitNOAT = true; }
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};
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} // end of namespace llvm
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#endif // MIPS_MACHINE_FUNCTION_INFO_H
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