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https://github.com/c64scene-ar/llvm-6502.git
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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
120 lines
6.0 KiB
LLVM
120 lines
6.0 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck -check-prefix=SI %s
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@lds = addrspace(3) global [512 x float] undef, align 4
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; SI-LABEL: @simple_write2st64_one_val_f32_0_1
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; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
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; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
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; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:1 [M0]
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; SI: s_endpgm
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define void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%in.gep = getelementptr float addrspace(1)* %in, i32 %x.i
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%val = load float addrspace(1)* %in.gep, align 4
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%arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
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store float %val, float addrspace(3)* %arrayidx0, align 4
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%add.x = add nsw i32 %x.i, 64
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%arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x
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store float %val, float addrspace(3)* %arrayidx1, align 4
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ret void
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}
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; SI-LABEL: @simple_write2st64_two_val_f32_2_5
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; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
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; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5 [M0]
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; SI: s_endpgm
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define void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%in.gep.0 = getelementptr float addrspace(1)* %in, i32 %x.i
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%in.gep.1 = getelementptr float addrspace(1)* %in.gep.0, i32 1
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%val0 = load float addrspace(1)* %in.gep.0, align 4
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%val1 = load float addrspace(1)* %in.gep.1, align 4
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%add.x.0 = add nsw i32 %x.i, 128
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%arrayidx0 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0
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store float %val0, float addrspace(3)* %arrayidx0, align 4
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%add.x.1 = add nsw i32 %x.i, 320
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%arrayidx1 = getelementptr inbounds [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1
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store float %val1, float addrspace(3)* %arrayidx1, align 4
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ret void
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}
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; SI-LABEL: @simple_write2st64_two_val_max_offset_f32
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; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
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; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255 [M0]
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; SI: s_endpgm
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define void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in, float addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%in.gep.0 = getelementptr float addrspace(1)* %in, i32 %x.i
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%in.gep.1 = getelementptr float addrspace(1)* %in.gep.0, i32 1
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%val0 = load float addrspace(1)* %in.gep.0, align 4
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%val1 = load float addrspace(1)* %in.gep.1, align 4
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%arrayidx0 = getelementptr inbounds float addrspace(3)* %lds, i32 %x.i
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store float %val0, float addrspace(3)* %arrayidx0, align 4
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%add.x = add nsw i32 %x.i, 16320
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%arrayidx1 = getelementptr inbounds float addrspace(3)* %lds, i32 %add.x
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store float %val1, float addrspace(3)* %arrayidx1, align 4
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ret void
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}
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; SI-LABEL: @simple_write2st64_two_val_max_offset_f64
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; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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; SI-DAG: v_add_i32_e32 [[VPTR:v[0-9]+]],
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; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127 [M0]
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; SI: s_endpgm
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define void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%in.gep.0 = getelementptr double addrspace(1)* %in, i32 %x.i
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%in.gep.1 = getelementptr double addrspace(1)* %in.gep.0, i32 1
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%val0 = load double addrspace(1)* %in.gep.0, align 8
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%val1 = load double addrspace(1)* %in.gep.1, align 8
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%add.x.0 = add nsw i32 %x.i, 256
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%arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.0
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store double %val0, double addrspace(3)* %arrayidx0, align 8
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%add.x.1 = add nsw i32 %x.i, 8128
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%arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x.1
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store double %val1, double addrspace(3)* %arrayidx1, align 8
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ret void
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}
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; SI-LABEL: @byte_size_only_divisible_64_write2st64_f64
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; SI-NOT: ds_write2st64_b64
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; SI: ds_write2_b64 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:0 offset1:8
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; SI: s_endpgm
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define void @byte_size_only_divisible_64_write2st64_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {
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%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
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%in.gep = getelementptr double addrspace(1)* %in, i32 %x.i
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%val = load double addrspace(1)* %in.gep, align 8
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%arrayidx0 = getelementptr inbounds double addrspace(3)* %lds, i32 %x.i
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store double %val, double addrspace(3)* %arrayidx0, align 8
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%add.x = add nsw i32 %x.i, 8
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%arrayidx1 = getelementptr inbounds double addrspace(3)* %lds, i32 %add.x
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store double %val, double addrspace(3)* %arrayidx1, align 8
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tgid.x() #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tgid.y() #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tidig.x() #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tidig.y() #1
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; Function Attrs: noduplicate nounwind
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declare void @llvm.AMDGPU.barrier.local() #2
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { noduplicate nounwind }
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