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llvm-6502/lib/Target/R600/AMDGPUFrameLowering.cpp
Tom Stellard df74b86e1e R600: Fix calculation of stack offset in AMDGPUFrameLowering
We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183568 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 20:52:05 +00:00

104 lines
3.0 KiB
C++

//===----------------------- AMDGPUFrameLowering.cpp ----------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//==-----------------------------------------------------------------------===//
//
// Interface to describe a layout of a stack frame on a AMDIL target machine
//
//===----------------------------------------------------------------------===//
#include "AMDGPUFrameLowering.h"
#include "AMDGPURegisterInfo.h"
#include "R600MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Instructions.h"
using namespace llvm;
AMDGPUFrameLowering::AMDGPUFrameLowering(StackDirection D, unsigned StackAl,
int LAO, unsigned TransAl)
: TargetFrameLowering(D, StackAl, LAO, TransAl) { }
AMDGPUFrameLowering::~AMDGPUFrameLowering() { }
unsigned AMDGPUFrameLowering::getStackWidth(const MachineFunction &MF) const {
// XXX: Hardcoding to 1 for now.
//
// I think the StackWidth should stored as metadata associated with the
// MachineFunction. This metadata can either be added by a frontend, or
// calculated by a R600 specific LLVM IR pass.
//
// The StackWidth determines how stack objects are laid out in memory.
// For a vector stack variable, like: int4 stack[2], the data will be stored
// in the following ways depending on the StackWidth.
//
// StackWidth = 1:
//
// T0.X = stack[0].x
// T1.X = stack[0].y
// T2.X = stack[0].z
// T3.X = stack[0].w
// T4.X = stack[1].x
// T5.X = stack[1].y
// T6.X = stack[1].z
// T7.X = stack[1].w
//
// StackWidth = 2:
//
// T0.X = stack[0].x
// T0.Y = stack[0].y
// T1.X = stack[0].z
// T1.Y = stack[0].w
// T2.X = stack[1].x
// T2.Y = stack[1].y
// T3.X = stack[1].z
// T3.Y = stack[1].w
//
// StackWidth = 4:
// T0.X = stack[0].x
// T0.Y = stack[0].y
// T0.Z = stack[0].z
// T0.W = stack[0].w
// T1.X = stack[1].x
// T1.Y = stack[1].y
// T1.Z = stack[1].z
// T1.W = stack[1].w
return 1;
}
/// \returns The number of registers allocated for \p FI.
int AMDGPUFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
int FI) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
unsigned Offset = 0;
int UpperBound = FI == -1 ? MFI->getNumObjects() : FI;
for (int i = MFI->getObjectIndexBegin(); i < UpperBound; ++i) {
unsigned Size = MFI->getObjectSize(i);
Offset += (Size / (getStackWidth(MF) * 4));
}
return Offset;
}
const TargetFrameLowering::SpillSlot *
AMDGPUFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
NumEntries = 0;
return 0;
}
void
AMDGPUFrameLowering::emitPrologue(MachineFunction &MF) const {
}
void
AMDGPUFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
}
bool
AMDGPUFrameLowering::hasFP(const MachineFunction &MF) const {
return false;
}