mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
57e6b2d1f3
Merge consecutive if-regions if they contain identical statements. Both transformations reduce number of branches. The transformation is guarded by a target-hook, and is currently enabled only for +R600, but the correctness has been tested on X86 target using a variety of CPU benchmarks. Patch by: Mei Ye git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187278 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
2.3 KiB
C++
72 lines
2.3 KiB
C++
//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
/// \brief The AMDGPU TargetMachine interface definition for hw codgen targets.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef AMDGPU_TARGET_MACHINE_H
|
|
#define AMDGPU_TARGET_MACHINE_H
|
|
|
|
#include "AMDGPUFrameLowering.h"
|
|
#include "AMDGPUInstrInfo.h"
|
|
#include "AMDGPUSubtarget.h"
|
|
#include "AMDILIntrinsicInfo.h"
|
|
#include "R600ISelLowering.h"
|
|
#include "llvm/ADT/OwningPtr.h"
|
|
#include "llvm/IR/DataLayout.h"
|
|
|
|
namespace llvm {
|
|
|
|
class AMDGPUTargetMachine : public LLVMTargetMachine {
|
|
|
|
AMDGPUSubtarget Subtarget;
|
|
const DataLayout Layout;
|
|
AMDGPUFrameLowering FrameLowering;
|
|
AMDGPUIntrinsicInfo IntrinsicInfo;
|
|
OwningPtr<AMDGPUInstrInfo> InstrInfo;
|
|
OwningPtr<AMDGPUTargetLowering> TLInfo;
|
|
const InstrItineraryData *InstrItins;
|
|
|
|
public:
|
|
AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS,
|
|
StringRef CPU, TargetOptions Options, Reloc::Model RM,
|
|
CodeModel::Model CM, CodeGenOpt::Level OL);
|
|
~AMDGPUTargetMachine();
|
|
virtual const AMDGPUFrameLowering *getFrameLowering() const {
|
|
return &FrameLowering;
|
|
}
|
|
virtual const AMDGPUIntrinsicInfo *getIntrinsicInfo() const {
|
|
return &IntrinsicInfo;
|
|
}
|
|
virtual const AMDGPUInstrInfo *getInstrInfo() const {
|
|
return InstrInfo.get();
|
|
}
|
|
virtual const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; }
|
|
virtual const AMDGPURegisterInfo *getRegisterInfo() const {
|
|
return &InstrInfo->getRegisterInfo();
|
|
}
|
|
virtual AMDGPUTargetLowering *getTargetLowering() const {
|
|
return TLInfo.get();
|
|
}
|
|
virtual const InstrItineraryData *getInstrItineraryData() const {
|
|
return InstrItins;
|
|
}
|
|
virtual const DataLayout *getDataLayout() const { return &Layout; }
|
|
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
|
|
|
|
/// \brief Register R600 analysis passes with a pass manager.
|
|
virtual void addAnalysisPasses(PassManagerBase &PM);
|
|
};
|
|
|
|
} // End namespace llvm
|
|
|
|
#endif // AMDGPU_TARGET_MACHINE_H
|