mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-22 07:32:48 +00:00
536bce219d
Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227089 91177308-0d34-0410-b5e6-96231b3b80d8
116 lines
3.7 KiB
LLVM
116 lines
3.7 KiB
LLVM
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
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; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
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define signext i1 @add_i1(i1 signext %a, i1 signext %b) {
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entry:
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; ALL-LABEL: add_i1:
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; ALL: addu $[[T0:[0-9]+]], $4, $5
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; ALL: sll $[[T0]], $[[T0]], 31
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; ALL: sra $2, $[[T0]], 31
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%r = add i1 %a, %b
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ret i1 %r
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}
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define signext i8 @add_i8(i8 signext %a, i8 signext %b) {
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entry:
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; ALL-LABEL: add_i8:
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; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5
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; NOT-R2-R6: sll $[[T0]], $[[T0]], 24
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; NOT-R2-R6: sra $2, $[[T0]], 24
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; R2-R6: addu $[[T0:[0-9]+]], $4, $5
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; R2-R6: seb $2, $[[T0:[0-9]+]]
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%r = add i8 %a, %b
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ret i8 %r
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}
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define signext i16 @add_i16(i16 signext %a, i16 signext %b) {
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entry:
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; ALL-LABEL: add_i16:
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; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5
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; NOT-R2-R6: sll $[[T0]], $[[T0]], 16
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; NOT-R2-R6: sra $2, $[[T0]], 16
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; R2-R6: addu $[[T0:[0-9]+]], $4, $5
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; R2-R6: seh $2, $[[T0:[0-9]+]]
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%r = add i16 %a, %b
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ret i16 %r
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}
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define signext i32 @add_i32(i32 signext %a, i32 signext %b) {
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entry:
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; ALL-LABEL: add_i32:
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; ALL: addu $2, $4, $5
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%r = add i32 %a, %b
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ret i32 %r
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}
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define signext i64 @add_i64(i64 signext %a, i64 signext %b) {
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entry:
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; ALL-LABEL: add_i64:
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; GP32: addu $3, $5, $7
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; GP32: sltu $[[T0:[0-9]+]], $3, $7
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; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6
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; GP32: addu $2, $4, $[[T1]]
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; GP64: daddu $2, $4, $5
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%r = add i64 %a, %b
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ret i64 %r
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}
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define signext i128 @add_i128(i128 signext %a, i128 signext %b) {
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entry:
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; ALL-LABEL: add_i128:
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; GP32: lw $[[T0:[0-9]+]], 28($sp)
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; GP32: addu $[[T1:[0-9]+]], $7, $[[T0]]
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; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; GP32: lw $[[T3:[0-9]+]], 24($sp)
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; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]]
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; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
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; GP32: lw $[[T7:[0-9]+]], 20($sp)
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; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
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; GP32: lw $[[T9:[0-9]+]], 16($sp)
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; GP32: addu $3, $5, $[[T8]]
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; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]]
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; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]]
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; GP32: addu $2, $4, $[[T11]]
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; GP32: move $4, $[[T5]]
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; GP32: move $5, $[[T1]]
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; GP64: daddu $3, $5, $7
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; GP64: sltu $[[T0:[0-9]+]], $3, $7
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; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6
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; GP64: daddu $2, $4, $[[T1]]
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%r = add i128 %a, %b
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ret i128 %r
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}
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