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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
4.1 KiB
C++
115 lines
4.1 KiB
C++
//===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMINSTRUCTIONINFO_H
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#define ARMINSTRUCTIONINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "ARMRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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/// ARMII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace ARMII {
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enum {
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//===------------------------------------------------------------------===//
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// Instruction Flags.
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//===------------------------------------------------------------------===//
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// This three-bit field describes the addressing mode used. Zero is unused
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// so that we can tell if we forgot to set a value.
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AddrModeMask = 0xf,
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AddrMode1 = 1,
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AddrMode2 = 2,
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AddrMode3 = 3,
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AddrMode4 = 4,
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AddrMode5 = 5,
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AddrModeT1 = 6,
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AddrModeT2 = 7,
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AddrModeT4 = 8,
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AddrModeTs = 9, // i8 * 4 for pc and sp relative data
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// Size* - Flags to keep track of the size of an instruction.
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SizeShift = 4,
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SizeMask = 7 << SizeShift,
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SizeSpecial = 1, // 0 byte pseudo or special case.
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Size8Bytes = 2,
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Size4Bytes = 3,
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Size2Bytes = 4,
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// IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
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// and store ops
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IndexModeShift = 7,
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IndexModeMask = 3 << IndexModeShift,
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IndexModePre = 1,
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IndexModePost = 2,
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// Opcode
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OpcodeShift = 9,
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OpcodeMask = 0xf << OpcodeShift
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};
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}
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class ARMInstrInfo : public TargetInstrInfo {
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const ARMRegisterInfo RI;
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public:
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ARMInstrInfo(const ARMSubtarget &STI);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass() const;
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/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
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/// instruction if it has one. This is used by codegen passes that update
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/// DWARF line number info as they modify the code.
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virtual unsigned getDWARF_LABELOpcode() const;
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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virtual bool isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg) const;
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virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
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virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
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virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables &LV) const;
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// Branch analysis.
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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std::vector<MachineOperand> &Cond) const;
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virtual void RemoveBranch(MachineBasicBlock &MBB) const;
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virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond) const;
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virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
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virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
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};
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}
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#endif
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