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382f7d717c
Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221341 91177308-0d34-0410-b5e6-96231b3b80d8
17 lines
320 B
ArmAsm
17 lines
320 B
ArmAsm
// RUN: llvm-mc -triple armv7-unknown-linux-gnueabi -mattr=+vfp3,-neon %s
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.fpu neon
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VAND d3, d5, d5
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vldr d21, [r7, #296]
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@ .thumb should not disable the prior .fpu neon
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.thumb
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vmov q4, q11 @ v4si
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str r6, [r7, #264]
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mov r6, r5
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vldr d21, [r7, #296]
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add r9, r7, #216
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fstmfdd sp!, {d8, d9, d10, d11, d12, d13, d14, d15}
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