mirror of
https://github.com/c64scene-ar/llvm-6502.git
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382f7d717c
Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221341 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
3.3 KiB
ArmAsm
74 lines
3.3 KiB
ArmAsm
@ RUN: llvm-mc < %s -triple armv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=ARM
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@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=THUMB
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@ RUN: not llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mcpu=cortex-m4 > %t 2> %t2
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@ RUN: FileCheck %s < %t --check-prefix=THUMB_V7EM
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@ RUN: FileCheck %s < %t2 --check-prefix=THUMB_V7EM-ERRORS
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@ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee]
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@ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b]
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@ THUMB_V7EM-ERRORS: error: invalid operand for instruction
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@ THUMB_V7EM-ERRORS-NEXT: vfma.f64 d16, d18, d17
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vfma.f64 d16, d18, d17
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@ ARM: vfma.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0xa2,0xee]
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@ THUMB: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a]
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@ THUMB_V7EM: vfma.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x00,0x1a]
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vfma.f32 s2, s4, s0
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@ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2]
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@ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c]
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@ THUMB_V7EM-ERRORS: error: invalid operand for instruction
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@ THUMB_V7EM-ERRORS-NEXT: vfma.f32 d16, d18, d17
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vfma.f32 d16, d18, d17
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@ ARM: vfma.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x08,0xf2]
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@ THUMB: vfma.f32 q2, q4, q0 @ encoding: [0x08,0xef,0x50,0x4c]
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@ THUMB_V7EM-ERRORS: error: instruction requires: NEON
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@ THUMB_V7EM-ERRORS-NEXT: vfma.f32 q2, q4, q0
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vfma.f32 q2, q4, q0
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@ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee]
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@ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b]
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@ THUMB_V7EM-ERRORS: error: invalid operand for instruction
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@ THUMB_V7EM-ERRORS-NEXT: vfnma.f64 d16, d18, d17
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vfnma.f64 d16, d18, d17
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@ ARM: vfnma.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0x92,0xee]
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@ THUMB: vfnma.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x40,0x1a]
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@ THUMB_V7EM: vfnma.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x40,0x1a]
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vfnma.f32 s2, s4, s0
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@ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee]
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@ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b]
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@ THUMB_V7EM-ERRORS: error: invalid operand for instruction
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@ THUMB_V7EM-ERRORS-NEXT: vfms.f64 d16, d18, d17
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vfms.f64 d16, d18, d17
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@ ARM: vfms.f32 s2, s4, s0 @ encoding: [0x40,0x1a,0xa2,0xee]
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@ THUMB: vfms.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x40,0x1a]
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@ THUMB_V7EM: vfms.f32 s2, s4, s0 @ encoding: [0xa2,0xee,0x40,0x1a]
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vfms.f32 s2, s4, s0
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@ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2]
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@ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c]
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@ THUMB_V7EM-ERRORS: error: invalid operand for instruction
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@ THUMB_V7EM-ERRORS-NEXT: vfms.f32 d16, d18, d17
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vfms.f32 d16, d18, d17
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@ ARM: vfms.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x28,0xf2]
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@ THUMB: vfms.f32 q2, q4, q0 @ encoding: [0x28,0xef,0x50,0x4c]
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@ THUMB_V7EM-ERRORS: error: instruction requires: NEON
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@ THUMB_V7EM-ERRORS-NEXT: vfms.f32 q2, q4, q0
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vfms.f32 q2, q4, q0
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@ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee]
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@ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b]
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@ THUMB_V7EM-ERRORS: error: invalid operand for instruction
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@ THUMB_V7EM-ERRORS-NEXT: vfnms.f64 d16, d18, d17
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vfnms.f64 d16, d18, d17
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@ ARM: vfnms.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0x92,0xee]
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@ THUMB: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a]
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@ THUMB_V7EM: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a]
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vfnms.f32 s2, s4, s0
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