mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
108 lines
3.9 KiB
TableGen
108 lines
3.9 KiB
TableGen
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class R600Reg <string name, bits<16> encoding> : Register<name> {
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let Namespace = "AMDGPU";
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let HWEncoding = encoding;
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}
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class R600RegWithChan <string name, bits<9> sel, string chan> :
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Register <name> {
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field bits<2> chan_encoding = !if(!eq(chan, "X"), 0,
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!if(!eq(chan, "Y"), 1,
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!if(!eq(chan, "Z"), 2,
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!if(!eq(chan, "W"), 3, 0))));
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let HWEncoding{8-0} = sel;
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let HWEncoding{10-9} = chan_encoding;
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let Namespace = "AMDGPU";
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}
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class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
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RegisterWithSubRegs<n, subregs> {
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let Namespace = "AMDGPU";
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let SubRegIndices = [sel_x, sel_y, sel_z, sel_w];
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let HWEncoding = encoding;
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}
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foreach Index = 0-127 in {
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foreach Chan = [ "X", "Y", "Z", "W" ] in {
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// 32-bit Temporary Registers
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def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>;
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// 32-bit Constant Registers (There are more than 128, this the number
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// that is currently supported.
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def C#Index#_#Chan : R600RegWithChan <"C"#Index#"."#Chan, Index, Chan>;
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}
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// 128-bit Temporary Registers
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def T#Index#_XYZW : R600Reg_128 <"T"#Index#".XYZW",
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[!cast<Register>("T"#Index#"_X"),
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!cast<Register>("T"#Index#"_Y"),
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!cast<Register>("T"#Index#"_Z"),
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!cast<Register>("T"#Index#"_W")],
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Index>;
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}
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// Array Base Register holding input in FS
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foreach Index = 448-464 in {
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def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>;
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}
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// Special Registers
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def ZERO : R600Reg<"0.0", 248>;
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def ONE : R600Reg<"1.0", 249>;
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def NEG_ONE : R600Reg<"-1.0", 249>;
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def ONE_INT : R600Reg<"1", 250>;
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def HALF : R600Reg<"0.5", 252>;
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def NEG_HALF : R600Reg<"-0.5", 252>;
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def ALU_LITERAL_X : R600Reg<"literal.x", 253>;
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def PV_X : R600Reg<"pv.x", 254>;
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def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;
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def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
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def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
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def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
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def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "ArrayBase%u", 448, 464))>;
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def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (interleave
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(interleave (sequence "C%u_X", 0, 127),
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(sequence "C%u_Z", 0, 127)),
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(interleave (sequence "C%u_Y", 0, 127),
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(sequence "C%u_W", 0, 127))))>;
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def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "T%u_X", 0, 127))>;
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def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "T%u_Y", 0, 127))>;
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def R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "T%u_Z", 0, 127))>;
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def R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (sequence "T%u_W", 0, 127))>;
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def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
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(add (interleave
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(interleave R600_TReg32_X, R600_TReg32_Z),
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(interleave R600_TReg32_Y, R600_TReg32_W)))>;
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def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
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R600_TReg32,
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R600_CReg32,
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R600_ArrayBase,
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ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF)>;
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def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
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PRED_SEL_OFF, PRED_SEL_ZERO, PRED_SEL_ONE)>;
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def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
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PREDICATE_BIT)>;
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def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
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(add (sequence "T%u_XYZW", 0, 127))> {
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let CopyCost = -1;
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}
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