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c004eec71b
(sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold the intermediate AND and the ADD into a single SUB. This fixes <rdar://problem/8449754>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114460 91177308-0d34-0410-b5e6-96231b3b80d8
15 lines
344 B
LLVM
15 lines
344 B
LLVM
; RUN: llc < %s -march=x86 | FileCheck %s
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; <rdar://problem/8449754>
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define i32 @add32carry(i32 %sum, i32 %x) nounwind readnone ssp {
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entry:
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; CHECK: sbbl %ecx, %ecx
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; CHECK-NOT: addl
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; CHECK: subl %ecx, %eax
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%add4 = add i32 %x, %sum
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%cmp = icmp ult i32 %add4, %x
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%inc = zext i1 %cmp to i32
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%z.0 = add i32 %add4, %inc
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ret i32 %z.0
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}
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