mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7f460203b0
purpose, and give it a custom SDNode subclass so that it doesn't need to have line number, column number, filename string, and directory string, all existing as individual SDNodes to be the operands. This was the only user of ISD::STRING, StringSDNode, etc., so remove those and some associated code. This makes stop-points considerably easier to read in -view-legalize-dags output, and reduces overhead (creating new nodes and copying std::strings into them) on code containing debugging information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52924 91177308-0d34-0410-b5e6-96231b3b80d8
718 lines
28 KiB
C++
718 lines
28 KiB
C++
//===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AlphaISelLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "AlphaISelLowering.h"
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#include "AlphaTargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Module.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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/// AddLiveIn - This helper function adds the specified physical register to the
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/// MachineFunction as a live in value. It also creates a corresponding virtual
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/// register for it.
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static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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TargetRegisterClass *RC) {
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
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MF.getRegInfo().addLiveIn(PReg, VReg);
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return VReg;
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}
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AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
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// Set up the TargetLowering object.
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//I am having problems with shr n ubyte 1
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setShiftAmountType(MVT::i64);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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setUsesGlobalOffsetTable(true);
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addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
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addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
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addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
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setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
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setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadXAction(ISD::ZEXTLOAD, MVT::i32, Expand);
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setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
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setLoadXAction(ISD::SEXTLOAD, MVT::i16, Expand);
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// setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::FREM, MVT::f32, Expand);
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setOperationAction(ISD::FREM, MVT::f64, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
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setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
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}
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setOperationAction(ISD::BSWAP , MVT::i64, Expand);
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setOperationAction(ISD::ROTL , MVT::i64, Expand);
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setOperationAction(ISD::ROTR , MVT::i64, Expand);
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setOperationAction(ISD::SREM , MVT::i64, Custom);
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setOperationAction(ISD::UREM , MVT::i64, Custom);
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setOperationAction(ISD::SDIV , MVT::i64, Custom);
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setOperationAction(ISD::UDIV , MVT::i64, Custom);
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// We don't support sin/cos/sqrt/pow
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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setOperationAction(ISD::FPOW , MVT::f32, Expand);
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setOperationAction(ISD::FPOW , MVT::f64, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Promote);
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setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
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// We don't have line number support yet.
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::LABEL, MVT::Other, Expand);
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// Not implemented yet.
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
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// We want to legalize GlobalAddress and ConstantPool and
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// ExternalSymbols nodes into the appropriate instructions to
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// materialize the address.
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
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setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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setOperationAction(ISD::VACOPY, MVT::Other, Custom);
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setOperationAction(ISD::VAARG, MVT::Other, Custom);
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setOperationAction(ISD::VAARG, MVT::i32, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::JumpTable, MVT::i64, Custom);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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setStackPointerRegisterToSaveRestore(Alpha::R30);
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addLegalFPImmediate(APFloat(+0.0)); //F31
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addLegalFPImmediate(APFloat(+0.0f)); //F31
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addLegalFPImmediate(APFloat(-0.0)); //-F31
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addLegalFPImmediate(APFloat(-0.0f)); //-F31
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setJumpBufSize(272);
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setJumpBufAlignment(16);
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computeRegisterProperties();
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}
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MVT AlphaTargetLowering::getSetCCResultType(const SDOperand &) const {
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return MVT::i64;
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}
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const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
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case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
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case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
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case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
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case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
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case AlphaISD::RelLit: return "Alpha::RelLit";
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case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
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case AlphaISD::CALL: return "Alpha::CALL";
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case AlphaISD::DivCall: return "Alpha::DivCall";
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case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
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case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
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case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
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}
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}
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static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
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MVT PtrVT = Op.getValueType();
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JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
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SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
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SDOperand Zero = DAG.getConstant(0, PtrVT);
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SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
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DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
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SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
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return Lo;
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}
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//http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
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//AA-PY8AC-TET1_html/callCH3.html#BLOCK21
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//For now, just use variable size stack frame format
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//In a standard call, the first six items are passed in registers $16
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//- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
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//of argument-to-register correspondence.) The remaining items are
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//collected in a memory argument list that is a naturally aligned
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//array of quadwords. In a standard call, this list, if present, must
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//be passed at 0(SP).
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//7 ... n 0(SP) ... (n-7)*8(SP)
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// //#define FP $15
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// //#define RA $26
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// //#define PV $27
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// //#define GP $29
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// //#define SP $30
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static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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int &VarArgsBase,
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int &VarArgsOffset) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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std::vector<SDOperand> ArgValues;
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SDOperand Root = Op.getOperand(0);
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AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
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AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
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unsigned args_int[] = {
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Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
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unsigned args_float[] = {
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Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
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for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
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SDOperand argt;
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MVT ObjectVT = Op.getValue(ArgNo).getValueType();
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SDOperand ArgVal;
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if (ArgNo < 6) {
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switch (ObjectVT.getSimpleVT()) {
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default:
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assert(false && "Invalid value type!");
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case MVT::f64:
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args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
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&Alpha::F8RCRegClass);
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ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
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break;
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case MVT::f32:
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args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
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&Alpha::F4RCRegClass);
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ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
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break;
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case MVT::i64:
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args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
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&Alpha::GPRCRegClass);
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ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
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break;
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}
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} else { //more args
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
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// Create the SelectionDAG nodes corresponding to a load
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//from this parameter
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
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ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
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}
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ArgValues.push_back(ArgVal);
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}
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// If the functions takes variable number of arguments, copy all regs to stack
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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if (isVarArg) {
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VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
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std::vector<SDOperand> LS;
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for (int i = 0; i < 6; ++i) {
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if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
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args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
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SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
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int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
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if (i == 0) VarArgsBase = FI;
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SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
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LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
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if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
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args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
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argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
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FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
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SDFI = DAG.getFrameIndex(FI, MVT::i64);
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LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0));
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}
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//Set up a token factor with all the stack traffic
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Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
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}
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ArgValues.push_back(Root);
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// Return the new list of results.
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return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
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ArgValues.size());
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}
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static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
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DAG.getNode(AlphaISD::GlobalRetAddr,
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MVT::i64),
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SDOperand());
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switch (Op.getNumOperands()) {
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default:
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assert(0 && "Do not know how to return this many arguments!");
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abort();
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case 1:
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break;
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//return SDOperand(); // ret void is legal
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case 3: {
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MVT ArgVT = Op.getOperand(1).getValueType();
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unsigned ArgReg;
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if (ArgVT.isInteger())
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ArgReg = Alpha::R0;
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else {
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assert(ArgVT.isFloatingPoint());
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ArgReg = Alpha::F0;
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}
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Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
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if (DAG.getMachineFunction().getRegInfo().liveout_empty())
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DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
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break;
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}
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}
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return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
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}
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std::pair<SDOperand, SDOperand>
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AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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bool RetSExt, bool RetZExt, bool isVarArg,
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unsigned CallingConv, bool isTailCall,
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SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG) {
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int NumBytes = 0;
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if (Args.size() > 6)
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NumBytes = (Args.size() - 6) * 8;
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Chain = DAG.getCALLSEQ_START(Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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std::vector<SDOperand> args_to_use;
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for (unsigned i = 0, e = Args.size(); i != e; ++i)
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{
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switch (getValueType(Args[i].Ty).getSimpleVT()) {
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default: assert(0 && "Unexpected ValueType for argument!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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// Promote the integer to 64 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].isSExt)
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Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
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else if (Args[i].isZExt)
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Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
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else
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Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
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break;
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case MVT::i64:
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case MVT::f64:
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case MVT::f32:
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break;
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}
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args_to_use.push_back(Args[i].Node);
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}
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std::vector<MVT> RetVals;
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MVT RetTyVT = getValueType(RetTy);
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MVT ActualRetTyVT = RetTyVT;
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if (RetTyVT.getSimpleVT() >= MVT::i1 && RetTyVT.getSimpleVT() <= MVT::i32)
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ActualRetTyVT = MVT::i64;
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if (RetTyVT != MVT::isVoid)
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RetVals.push_back(ActualRetTyVT);
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RetVals.push_back(MVT::Other);
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
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SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
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Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
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Chain = DAG.getCALLSEQ_END(Chain,
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DAG.getConstant(NumBytes, getPointerTy()),
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DAG.getConstant(0, getPointerTy()),
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SDOperand());
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SDOperand RetVal = TheCall;
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if (RetTyVT != ActualRetTyVT) {
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ISD::NodeType AssertKind = ISD::DELETED_NODE;
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if (RetSExt)
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AssertKind = ISD::AssertSext;
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else if (RetZExt)
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AssertKind = ISD::AssertZext;
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if (AssertKind != ISD::DELETED_NODE)
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RetVal = DAG.getNode(AssertKind, MVT::i64, RetVal,
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DAG.getValueType(RetTyVT));
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RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
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}
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return std::make_pair(RetVal, Chain);
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Wasn't expecting to be able to lower this!");
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
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VarArgsBase,
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VarArgsOffset);
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case ISD::RET: return LowerRET(Op,DAG);
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::SINT_TO_FP: {
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assert(Op.getOperand(0).getValueType() == MVT::i64 &&
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"Unhandled SINT_TO_FP type in custom expander!");
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SDOperand LD;
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bool isDouble = Op.getValueType() == MVT::f64;
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LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
|
|
SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
|
|
isDouble?MVT::f64:MVT::f32, LD);
|
|
return FP;
|
|
}
|
|
case ISD::FP_TO_SINT: {
|
|
bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
|
|
SDOperand src = Op.getOperand(0);
|
|
|
|
if (!isDouble) //Promote
|
|
src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
|
|
|
|
src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src);
|
|
}
|
|
case ISD::ConstantPool: {
|
|
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
|
|
Constant *C = CP->getConstVal();
|
|
SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
|
|
|
|
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
|
|
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
|
|
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
|
|
return Lo;
|
|
}
|
|
case ISD::GlobalTLSAddress:
|
|
assert(0 && "TLS not implemented for Alpha.");
|
|
case ISD::GlobalAddress: {
|
|
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
|
|
GlobalValue *GV = GSDN->getGlobal();
|
|
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
|
|
|
|
// if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
|
|
if (GV->hasInternalLinkage()) {
|
|
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
|
|
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
|
|
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
|
|
return Lo;
|
|
} else
|
|
return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
|
|
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
|
|
}
|
|
case ISD::ExternalSymbol: {
|
|
return DAG.getNode(AlphaISD::RelLit, MVT::i64,
|
|
DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
|
|
->getSymbol(), MVT::i64),
|
|
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
|
|
}
|
|
|
|
case ISD::UREM:
|
|
case ISD::SREM:
|
|
//Expand only on constant case
|
|
if (Op.getOperand(1).getOpcode() == ISD::Constant) {
|
|
MVT VT = Op.Val->getValueType(0);
|
|
SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
|
|
BuildUDIV(Op.Val, DAG, NULL) :
|
|
BuildSDIV(Op.Val, DAG, NULL);
|
|
Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
|
|
Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
|
|
return Tmp1;
|
|
}
|
|
//fall through
|
|
case ISD::SDIV:
|
|
case ISD::UDIV:
|
|
if (Op.getValueType().isInteger()) {
|
|
if (Op.getOperand(1).getOpcode() == ISD::Constant)
|
|
return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
|
|
: BuildUDIV(Op.Val, DAG, NULL);
|
|
const char* opstr = 0;
|
|
switch (Op.getOpcode()) {
|
|
case ISD::UREM: opstr = "__remqu"; break;
|
|
case ISD::SREM: opstr = "__remq"; break;
|
|
case ISD::UDIV: opstr = "__divqu"; break;
|
|
case ISD::SDIV: opstr = "__divq"; break;
|
|
}
|
|
SDOperand Tmp1 = Op.getOperand(0),
|
|
Tmp2 = Op.getOperand(1),
|
|
Addr = DAG.getExternalSymbol(opstr, MVT::i64);
|
|
return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
|
|
}
|
|
break;
|
|
|
|
case ISD::VAARG: {
|
|
SDOperand Chain = Op.getOperand(0);
|
|
SDOperand VAListP = Op.getOperand(1);
|
|
const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
|
|
|
SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0);
|
|
SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
|
|
DAG.getConstant(8, MVT::i64));
|
|
SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
|
|
Tmp, NULL, 0, MVT::i32);
|
|
SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
|
|
if (Op.getValueType().isFloatingPoint())
|
|
{
|
|
//if fp && Offset < 6*8, then subtract 6*8 from DataPtr
|
|
SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
|
|
DAG.getConstant(8*6, MVT::i64));
|
|
SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
|
|
DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
|
|
DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
|
|
}
|
|
|
|
SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
|
|
DAG.getConstant(8, MVT::i64));
|
|
SDOperand Update = DAG.getTruncStore(Offset.getValue(1), NewOffset,
|
|
Tmp, NULL, 0, MVT::i32);
|
|
|
|
SDOperand Result;
|
|
if (Op.getValueType() == MVT::i32)
|
|
Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
|
|
NULL, 0, MVT::i32);
|
|
else
|
|
Result = DAG.getLoad(Op.getValueType(), Update, DataPtr, NULL, 0);
|
|
return Result;
|
|
}
|
|
case ISD::VACOPY: {
|
|
SDOperand Chain = Op.getOperand(0);
|
|
SDOperand DestP = Op.getOperand(1);
|
|
SDOperand SrcP = Op.getOperand(2);
|
|
const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
|
|
const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
|
|
|
|
SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS, 0);
|
|
SDOperand Result = DAG.getStore(Val.getValue(1), Val, DestP, DestS, 0);
|
|
SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
|
|
DAG.getConstant(8, MVT::i64));
|
|
Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP, NULL,0, MVT::i32);
|
|
SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
|
|
DAG.getConstant(8, MVT::i64));
|
|
return DAG.getTruncStore(Val.getValue(1), Val, NPD, NULL, 0, MVT::i32);
|
|
}
|
|
case ISD::VASTART: {
|
|
SDOperand Chain = Op.getOperand(0);
|
|
SDOperand VAListP = Op.getOperand(1);
|
|
const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
|
|
|
// vastart stores the address of the VarArgsBase and VarArgsOffset
|
|
SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
|
|
SDOperand S1 = DAG.getStore(Chain, FR, VAListP, VAListS, 0);
|
|
SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
|
|
DAG.getConstant(8, MVT::i64));
|
|
return DAG.getTruncStore(S1, DAG.getConstant(VarArgsOffset, MVT::i64),
|
|
SA2, NULL, 0, MVT::i32);
|
|
}
|
|
case ISD::RETURNADDR:
|
|
return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
|
|
//FIXME: implement
|
|
case ISD::FRAMEADDR: break;
|
|
}
|
|
|
|
return SDOperand();
|
|
}
|
|
|
|
SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
|
|
SelectionDAG &DAG) {
|
|
assert(Op.getValueType() == MVT::i32 &&
|
|
Op.getOpcode() == ISD::VAARG &&
|
|
"Unknown node to custom promote!");
|
|
|
|
// The code in LowerOperation already handles i32 vaarg
|
|
return LowerOperation(Op, DAG);
|
|
}
|
|
|
|
|
|
//Inline Asm
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
/// constraint it is for this target.
|
|
AlphaTargetLowering::ConstraintType
|
|
AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
|
|
if (Constraint.size() == 1) {
|
|
switch (Constraint[0]) {
|
|
default: break;
|
|
case 'f':
|
|
case 'r':
|
|
return C_RegisterClass;
|
|
}
|
|
}
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
}
|
|
|
|
std::vector<unsigned> AlphaTargetLowering::
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
|
MVT VT) const {
|
|
if (Constraint.size() == 1) {
|
|
switch (Constraint[0]) {
|
|
default: break; // Unknown constriant letter
|
|
case 'f':
|
|
return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
|
|
Alpha::F3 , Alpha::F4 , Alpha::F5 ,
|
|
Alpha::F6 , Alpha::F7 , Alpha::F8 ,
|
|
Alpha::F9 , Alpha::F10, Alpha::F11,
|
|
Alpha::F12, Alpha::F13, Alpha::F14,
|
|
Alpha::F15, Alpha::F16, Alpha::F17,
|
|
Alpha::F18, Alpha::F19, Alpha::F20,
|
|
Alpha::F21, Alpha::F22, Alpha::F23,
|
|
Alpha::F24, Alpha::F25, Alpha::F26,
|
|
Alpha::F27, Alpha::F28, Alpha::F29,
|
|
Alpha::F30, Alpha::F31, 0);
|
|
case 'r':
|
|
return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
|
|
Alpha::R3 , Alpha::R4 , Alpha::R5 ,
|
|
Alpha::R6 , Alpha::R7 , Alpha::R8 ,
|
|
Alpha::R9 , Alpha::R10, Alpha::R11,
|
|
Alpha::R12, Alpha::R13, Alpha::R14,
|
|
Alpha::R15, Alpha::R16, Alpha::R17,
|
|
Alpha::R18, Alpha::R19, Alpha::R20,
|
|
Alpha::R21, Alpha::R22, Alpha::R23,
|
|
Alpha::R24, Alpha::R25, Alpha::R26,
|
|
Alpha::R27, Alpha::R28, Alpha::R29,
|
|
Alpha::R30, Alpha::R31, 0);
|
|
}
|
|
}
|
|
|
|
return std::vector<unsigned>();
|
|
}
|
|
//===----------------------------------------------------------------------===//
|
|
// Other Lowering Code
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
MachineBasicBlock *
|
|
AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
MachineBasicBlock *BB) {
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
assert((MI->getOpcode() == Alpha::CAS32 ||
|
|
MI->getOpcode() == Alpha::CAS64 ||
|
|
MI->getOpcode() == Alpha::LAS32 ||
|
|
MI->getOpcode() == Alpha::LAS64 ||
|
|
MI->getOpcode() == Alpha::SWAP32 ||
|
|
MI->getOpcode() == Alpha::SWAP64) &&
|
|
"Unexpected instr type to insert");
|
|
|
|
bool is32 = MI->getOpcode() == Alpha::CAS32 ||
|
|
MI->getOpcode() == Alpha::LAS32 ||
|
|
MI->getOpcode() == Alpha::SWAP32;
|
|
|
|
//Load locked store conditional for atomic ops take on the same form
|
|
//start:
|
|
//ll
|
|
//do stuff (maybe branch to exit)
|
|
//sc
|
|
//test sc and maybe branck to start
|
|
//exit:
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
ilist<MachineBasicBlock>::iterator It = BB;
|
|
++It;
|
|
|
|
MachineBasicBlock *thisMBB = BB;
|
|
MachineBasicBlock *llscMBB = new MachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
|
|
|
|
sinkMBB->transferSuccessors(thisMBB);
|
|
|
|
MachineFunction *F = BB->getParent();
|
|
F->getBasicBlockList().insert(It, llscMBB);
|
|
F->getBasicBlockList().insert(It, sinkMBB);
|
|
|
|
BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB);
|
|
|
|
unsigned reg_res = MI->getOperand(0).getReg(),
|
|
reg_ptr = MI->getOperand(1).getReg(),
|
|
reg_v2 = MI->getOperand(2).getReg(),
|
|
reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
|
|
|
|
BuildMI(llscMBB, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
|
|
reg_res).addImm(0).addReg(reg_ptr);
|
|
switch (MI->getOpcode()) {
|
|
case Alpha::CAS32:
|
|
case Alpha::CAS64: {
|
|
unsigned reg_cmp
|
|
= F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
|
|
BuildMI(llscMBB, TII->get(Alpha::CMPEQ), reg_cmp)
|
|
.addReg(reg_v2).addReg(reg_res);
|
|
BuildMI(llscMBB, TII->get(Alpha::BEQ))
|
|
.addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
|
|
BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
|
|
.addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
|
|
break;
|
|
}
|
|
case Alpha::LAS32:
|
|
case Alpha::LAS64: {
|
|
BuildMI(llscMBB, TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
|
|
.addReg(reg_res).addReg(reg_v2);
|
|
break;
|
|
}
|
|
case Alpha::SWAP32:
|
|
case Alpha::SWAP64: {
|
|
BuildMI(llscMBB, TII->get(Alpha::BISr), reg_store)
|
|
.addReg(reg_v2).addReg(reg_v2);
|
|
break;
|
|
}
|
|
}
|
|
BuildMI(llscMBB, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
|
|
.addReg(reg_store).addImm(0).addReg(reg_ptr);
|
|
BuildMI(llscMBB, TII->get(Alpha::BEQ))
|
|
.addImm(0).addReg(reg_store).addMBB(llscMBB);
|
|
BuildMI(llscMBB, TII->get(Alpha::BR)).addMBB(sinkMBB);
|
|
|
|
thisMBB->addSuccessor(llscMBB);
|
|
llscMBB->addSuccessor(llscMBB);
|
|
llscMBB->addSuccessor(sinkMBB);
|
|
delete MI; // The pseudo instruction is gone now.
|
|
|
|
return sinkMBB;
|
|
}
|