mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
399 lines
12 KiB
LLVM
399 lines
12 KiB
LLVM
; RUN: opt < %s -instcombine -S
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128:n8:16:32"
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target triple = "i386-apple-darwin10.0"
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define i32 @test0(i8 %tmp2) ssp {
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entry:
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%tmp3 = zext i8 %tmp2 to i32
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%tmp8 = lshr i32 %tmp3, 6
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%tmp9 = lshr i32 %tmp3, 7
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%tmp10 = xor i32 %tmp9, 67108858
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%tmp11 = xor i32 %tmp10, %tmp8
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%tmp12 = xor i32 %tmp11, 0
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ret i32 %tmp12
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}
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; PR4905
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define <2 x i64> @test1(<2 x i64> %x, <2 x i64> %y) nounwind {
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entry:
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%conv.i94 = bitcast <2 x i64> %y to <4 x i32> ; <<4 x i32>> [#uses=1]
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%sub.i97 = sub <4 x i32> %conv.i94, undef ; <<4 x i32>> [#uses=1]
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%conv3.i98 = bitcast <4 x i32> %sub.i97 to <2 x i64> ; <<2 x i64>> [#uses=2]
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%conv2.i86 = bitcast <2 x i64> %conv3.i98 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%cmp.i87 = icmp sgt <4 x i32> undef, %conv2.i86 ; <<4 x i1>> [#uses=1]
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%sext.i88 = sext <4 x i1> %cmp.i87 to <4 x i32> ; <<4 x i32>> [#uses=1]
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%conv3.i89 = bitcast <4 x i32> %sext.i88 to <2 x i64> ; <<2 x i64>> [#uses=1]
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%and.i = and <2 x i64> %conv3.i89, %conv3.i98 ; <<2 x i64>> [#uses=1]
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%or.i = or <2 x i64> zeroinitializer, %and.i ; <<2 x i64>> [#uses=1]
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%conv2.i43 = bitcast <2 x i64> %or.i to <4 x i32> ; <<4 x i32>> [#uses=1]
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%sub.i = sub <4 x i32> zeroinitializer, %conv2.i43 ; <<4 x i32>> [#uses=1]
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%conv3.i44 = bitcast <4 x i32> %sub.i to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %conv3.i44
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}
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; PR4908
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define void @test2(<1 x i16>* nocapture %b, i32* nocapture %c) nounwind ssp {
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entry:
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%arrayidx = getelementptr inbounds <1 x i16>, <1 x i16>* %b, i64 undef ; <<1 x i16>*>
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%tmp2 = load <1 x i16>, <1 x i16>* %arrayidx ; <<1 x i16>> [#uses=1]
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%tmp6 = bitcast <1 x i16> %tmp2 to i16 ; <i16> [#uses=1]
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%tmp7 = zext i16 %tmp6 to i32 ; <i32> [#uses=1]
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%ins = or i32 0, %tmp7 ; <i32> [#uses=1]
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%arrayidx20 = getelementptr inbounds i32, i32* %c, i64 undef ; <i32*> [#uses=1]
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store i32 %ins, i32* %arrayidx20
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ret void
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}
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; PR5262
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@tmp2 = global i64 0 ; <i64*> [#uses=1]
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declare void @use(i64) nounwind
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define void @foo(i1) nounwind align 2 {
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; <label>:1
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br i1 %0, label %2, label %3
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; <label>:2 ; preds = %1
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br label %3
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; <label>:3 ; preds = %2, %1
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%4 = phi i8 [ 1, %2 ], [ 0, %1 ] ; <i8> [#uses=1]
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%5 = icmp eq i8 %4, 0 ; <i1> [#uses=1]
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%6 = load i64, i64* @tmp2, align 8 ; <i64> [#uses=1]
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%7 = select i1 %5, i64 0, i64 %6 ; <i64> [#uses=1]
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br label %8
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; <label>:8 ; preds = %3
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call void @use(i64 %7)
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ret void
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}
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%t0 = type { i32, i32 }
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%t1 = type { i32, i32, i32, i32, i32* }
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declare %t0* @bar2(i64)
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define void @bar3(i1, i1) nounwind align 2 {
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; <label>:2
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br i1 %1, label %10, label %3
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; <label>:3 ; preds = %2
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%4 = getelementptr inbounds %t0, %t0* null, i64 0, i32 1 ; <i32*> [#uses=0]
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%5 = getelementptr inbounds %t1, %t1* null, i64 0, i32 4 ; <i32**> [#uses=1]
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%6 = load i32*, i32** %5, align 8 ; <i32*> [#uses=1]
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%7 = icmp ne i32* %6, null ; <i1> [#uses=1]
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%8 = zext i1 %7 to i32 ; <i32> [#uses=1]
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%9 = add i32 %8, 0 ; <i32> [#uses=1]
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br label %10
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; <label>:10 ; preds = %3, %2
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%11 = phi i32 [ %9, %3 ], [ 0, %2 ] ; <i32> [#uses=1]
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br i1 %1, label %12, label %13
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; <label>:12 ; preds = %10
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br label %13
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; <label>:13 ; preds = %12, %10
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%14 = zext i32 %11 to i64 ; <i64> [#uses=1]
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%15 = tail call %t0* @bar2(i64 %14) nounwind ; <%0*> [#uses=0]
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ret void
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}
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; PR5262
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; Make sure the PHI node gets put in a place where all of its operands dominate
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; it.
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define i64 @test4(i1 %c, i64* %P) nounwind align 2 {
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BB0:
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br i1 %c, label %BB1, label %BB2
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BB1:
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br label %BB2
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BB2:
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%v5_ = phi i1 [ true, %BB0], [false, %BB1]
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%v6 = load i64, i64* %P
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br label %l8
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l8:
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br label %l10
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l10:
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%v11 = select i1 %v5_, i64 0, i64 %v6
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ret i64 %v11
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}
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; PR5471
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define i32 @test5a() {
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ret i32 0
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}
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define void @test5() {
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store i1 true, i1* undef
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%r = invoke i32 @test5a() to label %exit unwind label %unwind
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unwind:
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%exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
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cleanup
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br label %exit
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exit:
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ret void
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}
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; PR5673
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@test6g = external global i32*
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define arm_aapcs_vfpcc i32 @test6(i32 %argc, i8** %argv) nounwind {
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entry:
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store i32* getelementptr (i32* bitcast (i32 (i32, i8**)* @test6 to i32*), i32 -2048), i32** @test6g, align 4
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unreachable
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}
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; PR5827
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%class.RuleBasedBreakIterator = type { i64 ()* }
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%class.UStack = type { i8** }
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define i32 @_ZN22RuleBasedBreakIterator15checkDictionaryEi(%class.RuleBasedBreakIterator* %this, i32 %x) align 2 {
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entry:
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%breaks = alloca %class.UStack, align 4 ; <%class.UStack*> [#uses=3]
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call void @_ZN6UStackC1Ei(%class.UStack* %breaks, i32 0)
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%tobool = icmp ne i32 %x, 0 ; <i1> [#uses=1]
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br i1 %tobool, label %cond.end, label %cond.false
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terminate.handler: ; preds = %ehcleanup
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%exc = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
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cleanup
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call void @_ZSt9terminatev() noreturn nounwind
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unreachable
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ehcleanup: ; preds = %cond.false
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%exc1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
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catch i8* null
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invoke void @_ZN6UStackD1Ev(%class.UStack* %breaks)
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to label %cont unwind label %terminate.handler
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cont: ; preds = %ehcleanup
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resume { i8*, i32 } %exc1
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cond.false: ; preds = %entry
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%tmp4 = getelementptr inbounds %class.RuleBasedBreakIterator, %class.RuleBasedBreakIterator* %this, i32 0, i32 0 ; <i64 ()**> [#uses=1]
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%tmp5 = load i64 ()*, i64 ()** %tmp4 ; <i64 ()*> [#uses=1]
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%call = invoke i64 %tmp5()
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to label %cond.end unwind label %ehcleanup ; <i64> [#uses=1]
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cond.end: ; preds = %cond.false, %entry
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%cond = phi i64 [ 0, %entry ], [ %call, %cond.false ] ; <i64> [#uses=1]
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%conv = trunc i64 %cond to i32 ; <i32> [#uses=1]
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call void @_ZN6UStackD1Ev(%class.UStack* %breaks)
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ret i32 %conv
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}
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declare void @_ZN6UStackC1Ei(%class.UStack*, i32)
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declare void @_ZN6UStackD1Ev(%class.UStack*)
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declare i32 @__gxx_personality_v0(...)
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declare void @_ZSt9terminatev()
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declare void @_Unwind_Resume_or_Rethrow(i8*)
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; rdar://7590304
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define i8* @test10(i8* %self, i8* %tmp3) {
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entry:
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store i1 true, i1* undef
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store i1 true, i1* undef
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invoke void @test10a()
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to label %invoke.cont unwind label %try.handler ; <i8*> [#uses=0]
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invoke.cont: ; preds = %entry
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unreachable
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try.handler: ; preds = %entry
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%exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
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catch i8* null
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ret i8* %self
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}
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define void @test10a() {
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ret void
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}
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; PR6193
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define i32 @test11(i32 %aMaskWidth, i8 %aStride) nounwind {
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entry:
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%conv41 = sext i8 %aStride to i32
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%neg = xor i32 %conv41, -1
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%and42 = and i32 %aMaskWidth, %neg
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%and47 = and i32 130, %conv41
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%or = or i32 %and42, %and47
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ret i32 %or
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}
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; PR6503
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define void @test12(i32* %A) nounwind {
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entry:
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%tmp1 = load i32, i32* %A
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%cmp = icmp ugt i32 1, %tmp1 ; <i1> [#uses=1]
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%conv = zext i1 %cmp to i32 ; <i32> [#uses=1]
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%tmp2 = load i32, i32* %A
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%cmp3 = icmp ne i32 %tmp2, 0 ; <i1> [#uses=1]
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%conv4 = zext i1 %cmp3 to i32 ; <i32> [#uses=1]
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%or = or i32 %conv, %conv4 ; <i32> [#uses=1]
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%cmp5 = icmp ugt i32 undef, %or ; <i1> [#uses=1]
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%conv6 = zext i1 %cmp5 to i32 ; <i32> [#uses=0]
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ret void
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}
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%s1 = type { %s2, %s2, [6 x %s2], i32, i32, i32, [1 x i32], [0 x i8] }
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%s2 = type { i64 }
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define void @test13() nounwind ssp {
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entry:
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%0 = getelementptr inbounds %s1, %s1* null, i64 0, i32 2, i64 0, i32 0
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%1 = bitcast i64* %0 to i32*
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%2 = getelementptr inbounds %s1, %s1* null, i64 0, i32 2, i64 1, i32 0
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%.pre = load i32, i32* %1, align 8
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%3 = lshr i32 %.pre, 19
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%brmerge = or i1 undef, undef
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%4 = and i32 %3, 3
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%5 = add nsw i32 %4, 1
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%6 = shl i32 %5, 19
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%7 = add i32 %6, 1572864
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%8 = and i32 %7, 1572864
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%9 = load i64, i64* %2, align 8
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%trunc156 = trunc i64 %9 to i32
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%10 = and i32 %trunc156, -1537
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%11 = and i32 %10, -6145
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%12 = or i32 %11, 2048
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%13 = and i32 %12, -24577
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%14 = or i32 %13, 16384
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%15 = or i32 %14, 98304
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store i32 %15, i32* undef, align 8
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%16 = and i32 %15, -1572865
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%17 = or i32 %16, %8
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store i32 %17, i32* undef, align 8
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%18 = and i32 %17, -449
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%19 = or i32 %18, 64
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store i32 %19, i32* undef, align 8
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unreachable
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}
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; PR8807
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declare i32 @test14f(i8* (i8*)*) nounwind
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define void @test14() nounwind readnone {
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entry:
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%tmp = bitcast i32 (i8* (i8*)*)* @test14f to i32 (i32*)*
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%call10 = call i32 %tmp(i32* byval undef)
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ret void
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}
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; PR8896
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@g_54 = external global [7 x i16]
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define void @test15(i32* %p_92) nounwind {
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entry:
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%0 = load i32, i32* %p_92, align 4
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%1 = icmp ne i32 %0, 0
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%2 = zext i1 %1 to i32
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%3 = call i32 @func_14() nounwind
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%4 = trunc i32 %3 to i16
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%5 = sext i16 %4 to i32
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%6 = trunc i32 %5 to i16
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br i1 undef, label %"3", label %"5"
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"3": ; preds = %entry
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%7 = sext i16 %6 to i32
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%8 = ashr i32 %7, -1649554541
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%9 = trunc i32 %8 to i16
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br label %"5"
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"5": ; preds = %"3", %entry
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%10 = phi i16 [ %9, %"3" ], [ %6, %entry ]
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%11 = sext i16 %10 to i32
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%12 = xor i32 %2, %11
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%13 = sext i32 %12 to i64
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%14 = icmp ne i64 %13, 0
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br i1 %14, label %return, label %"7"
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"7": ; preds = %"5"
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ret void
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return: ; preds = %"5"
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ret void
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}
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declare i32 @func_14()
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define double @test16(i32 %a) nounwind {
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%cmp = icmp slt i32 %a, 2
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%select = select i1 %cmp, double 2.000000e+00, double 3.141592e+00
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ret double %select
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}
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; PR8983
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%struct.basic_ios = type { i8 }
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define %struct.basic_ios *@test17() ssp {
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entry:
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%add.ptr.i = getelementptr i8, i8* null, i64 undef
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%0 = bitcast i8* %add.ptr.i to %struct.basic_ios*
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ret %struct.basic_ios* %0
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}
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; PR9013
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define void @test18() nounwind ssp {
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entry:
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%l_197.0 = phi i32 [ 0, %entry ], [ %sub.i, %for.inc ]
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br label %for.inc
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for.inc: ; preds = %for.cond
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%conv = and i32 %l_197.0, 255
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%sub.i = add nsw i32 %conv, -1
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br label %for.cond
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return: ; No predecessors!
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ret void
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}
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; PR11275
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declare void @test18b() noreturn
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declare void @test18foo(double**)
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declare void @test18a() noreturn
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define fastcc void @test18x(i8* %t0, i1 %b) uwtable align 2 {
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entry:
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br i1 %b, label %e1, label %e2
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e1:
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%t2 = bitcast i8* %t0 to double**
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invoke void @test18b() noreturn
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to label %u unwind label %lpad
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e2:
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%t4 = bitcast i8* %t0 to double**
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invoke void @test18a() noreturn
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to label %u unwind label %lpad
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lpad:
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%t5 = phi double** [ %t2, %e1 ], [ %t4, %e2 ]
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%lpad.nonloopexit262 = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
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cleanup
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call void @test18foo(double** %t5)
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unreachable
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u:
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unreachable
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}
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