llvm-6502/lib/Target/ARM/Disassembler
Johnny Chen c3281c10c9 A7.3 register encoding
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 22:57:07 +00:00
..
ARMDisassembler.cpp Fixed the t2PLD and friends disassembly and add two test cases. 2011-03-26 01:32:48 +00:00
ARMDisassembler.h Better error handling of invalid IT mask '0000', instead of just asserting. 2010-04-19 23:02:58 +00:00
ARMDisassemblerCore.cpp A7.3 register encoding 2011-04-05 22:57:07 +00:00
ARMDisassemblerCore.h RFE encoding should also specify the "should be" encoding bits. 2011-04-04 23:39:08 +00:00
CMakeLists.txt CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86. 2010-12-29 03:59:27 +00:00
Makefile
ThumbDisassemblerCore.h Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases. 2011-03-28 18:41:58 +00:00