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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53272 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
3.7 KiB
C++
115 lines
3.7 KiB
C++
//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MipsISELLOWERING_H
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#define MipsISELLOWERING_H
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include "Mips.h"
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#include "MipsSubtarget.h"
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namespace llvm {
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namespace MipsISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+Mips::INSTRUCTION_LIST_END,
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// Jump and link (call)
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JmpLink,
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// Get the Higher 16 bits from a 32-bit immediate
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// No relation with Mips Hi register
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Hi,
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// Get the Lower 16 bits from a 32-bit immediate
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// No relation with Mips Lo register
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Lo,
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// Select CC Pseudo Instruction
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SelectCC,
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// Floating Point Branch Conditional
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FPBrcond,
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// Floating Point Compare
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FPCmp,
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// Return
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Ret
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class MipsTargetLowering : public TargetLowering
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{
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// FrameIndex for return slot.
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int ReturnAddrIndex;
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// const MipsSubtarget &MipsSubTarget;
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public:
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explicit MipsTargetLowering(MipsTargetMachine &TM);
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/// LowerOperation - Provide custom lowering hooks for some operations.
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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/// getTargetNodeName - This method returns the name of a target specific
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// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getSetCCResultType - get the ISD::SETCC result ValueType
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MVT getSetCCResultType(const SDOperand &) const;
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private:
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// Subtarget Info
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const MipsSubtarget *Subtarget;
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// Lower Operand helpers
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SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
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SDNode *LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode*TheCall,
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unsigned CallingConv, SelectionDAG &DAG);
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SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
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// Lower Operand specifics
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SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG);
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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// Inline asm support
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const;
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const;
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};
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}
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#endif // MipsISELLOWERING_H
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