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https://github.com/c64scene-ar/llvm-6502.git
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225ca9cdd7
important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
121 lines
3.6 KiB
C++
121 lines
3.6 KiB
C++
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Mips target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsTargetAsmInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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using namespace llvm;
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// Register the target.
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static RegisterTarget<MipsTargetMachine> X("mips", " Mips");
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static RegisterTarget<MipselTargetMachine> Y("mipsel", " Mipsel");
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const TargetAsmInfo *MipsTargetMachine::
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createTargetAsmInfo() const
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{
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return new MipsTargetAsmInfo(*this);
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}
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// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
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// The stack is always 8 byte aligned
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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// offset from the stack/frame pointer, so StackGrowsUp is used.
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// Using CodeModel::Large enables different CALL behavior.
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MipsTargetMachine::
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MipsTargetMachine(const Module &M, const std::string &FS, bool isLittle=false):
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Subtarget(*this, M, FS, isLittle),
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DataLayout(isLittle ? std::string("e-p:32:32:32") :
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std::string("E-p:32:32:32")),
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InstrInfo(*this),
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FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0),
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TLInfo(*this)
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{
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if (getRelocationModel() != Reloc::Static)
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setRelocationModel(Reloc::PIC_);
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if (getCodeModel() == CodeModel::Default)
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setCodeModel(CodeModel::Small);
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}
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MipselTargetMachine::
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MipselTargetMachine(const Module &M, const std::string &FS) :
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MipsTargetMachine(M, FS, true) {}
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// return 0 and must specify -march to gen MIPS code.
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unsigned MipsTargetMachine::
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getModuleMatchQuality(const Module &M)
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{
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// We strongly match "mips*-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 5 && std::string(TT.begin(), TT.begin()+5) == "mips-")
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return 20;
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if (TT.size() >= 13 && std::string(TT.begin(),
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TT.begin()+13) == "mipsallegrex-")
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return 20;
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return 0;
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}
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// return 0 and must specify -march to gen MIPSEL code.
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unsigned MipselTargetMachine::
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getModuleMatchQuality(const Module &M)
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{
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// We strongly match "mips*el-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 7 && std::string(TT.begin(), TT.begin()+7) == "mipsel-")
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return 20;
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if (TT.size() >= 15 && std::string(TT.begin(),
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TT.begin()+15) == "mipsallegrexel-")
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return 20;
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if (TT.size() == 3 && std::string(TT.begin(), TT.begin()+3) == "psp")
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return 20;
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return 0;
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}
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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bool MipsTargetMachine::
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addInstSelector(PassManagerBase &PM, bool Fast)
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{
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PM.add(createMipsISelDag(*this));
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return false;
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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// print out the code after the passes.
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bool MipsTargetMachine::
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addPreEmitPass(PassManagerBase &PM, bool Fast)
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{
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PM.add(createMipsDelaySlotFillerPass(*this));
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return true;
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}
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// Implements the AssemblyEmitter for the target. Must return
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// true if AssemblyEmitter is supported
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bool MipsTargetMachine::
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addAssemblyEmitter(PassManagerBase &PM, bool Fast,
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std::ostream &Out)
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{
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// Output assembly language.
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PM.add(createMipsCodePrinterPass(Out, *this));
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return false;
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}
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