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This is a skeleton for a pre-RA MachineInstr scheduler strategy. Currently it only tries to expose more parallelism for ALU instructions (this also makes the distribution of GPR channels more uniform and increases the chances of ALU instructions to be packed together in a single VLIW group). Also it tries to reduce clause switching by grouping instruction of the same kind (ALU/FETCH/CF) together. Vincent Lejeune: - Support for VLIW4 Slot assignement - Recomputation of ScheduleDAG to get more parallelism opportunities Tom Stellard: - Fix assertion failure when trying to determine an instruction's slot based on its destination register's class - Fix some compiler warnings Vincent Lejeune: [v2] - Remove recomputation of ScheduleDAG (will be provided in a later patch) - Improve estimation of an ALU clause size so that heuristic does not emit cf instructions at the wrong position. - Make schedule heuristic smarter using SUnit Depth - Take constant read limitations into account Vincent Lejeune: [v3] - Fix some uninitialized values in ConstPair - Add asserts to ensure an ALU slot is always populated git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176498 91177308-0d34-0410-b5e6-96231b3b80d8
168 lines
5.1 KiB
C++
168 lines
5.1 KiB
C++
//===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief The AMDGPU target machine contains all of the hardware specific
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/// information needed to emit code for R600 and SI GPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetMachine.h"
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#include "AMDGPU.h"
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#include "R600ISelLowering.h"
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#include "R600InstrInfo.h"
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#include "R600MachineScheduler.h"
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#include "SIISelLowering.h"
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#include "SIInstrInfo.h"
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#include "llvm/Analysis/Passes.h"
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#include "llvm/Analysis/Verifier.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_os_ostream.h"
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#include "llvm/Transforms/IPO.h"
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#include "llvm/Transforms/Scalar.h"
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#include <llvm/CodeGen/Passes.h>
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using namespace llvm;
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extern "C" void LLVMInitializeR600Target() {
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// Register the target
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RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
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}
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static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
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return new ScheduleDAGMI(C, new R600SchedStrategy());
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}
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static MachineSchedRegistry
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SchedCustomRegistry("r600", "Run R600's custom scheduler",
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createR600MachineScheduler);
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AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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TargetOptions Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OptLevel
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)
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:
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LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
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Subtarget(TT, CPU, FS),
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Layout(Subtarget.getDataLayout()),
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FrameLowering(TargetFrameLowering::StackGrowsUp,
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Subtarget.device()->getStackAlignment(), 0),
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IntrinsicInfo(this),
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InstrItins(&Subtarget.getInstrItineraryData()) {
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// TLInfo uses InstrInfo so it must be initialized after.
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if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
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InstrInfo = new R600InstrInfo(*this);
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TLInfo = new R600TargetLowering(*this);
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} else {
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InstrInfo = new SIInstrInfo(*this);
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TLInfo = new SITargetLowering(*this);
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}
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}
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AMDGPUTargetMachine::~AMDGPUTargetMachine() {
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}
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namespace {
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class AMDGPUPassConfig : public TargetPassConfig {
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public:
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AMDGPUPassConfig(AMDGPUTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
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enablePass(&MachineSchedulerID);
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MachineSchedRegistry::setDefault(createR600MachineScheduler);
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}
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}
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AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
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return getTM<AMDGPUTargetMachine>();
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}
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virtual bool addPreISel();
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virtual bool addInstSelector();
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virtual bool addPreRegAlloc();
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virtual bool addPostRegAlloc();
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virtual bool addPreSched2();
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virtual bool addPreEmitPass();
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};
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} // End of anonymous namespace
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TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new AMDGPUPassConfig(this, PM);
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}
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bool
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AMDGPUPassConfig::addPreISel() {
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
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addPass(createAMDGPUStructurizeCFGPass());
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addPass(createSIAnnotateControlFlowPass());
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}
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return false;
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}
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bool AMDGPUPassConfig::addInstSelector() {
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addPass(createAMDGPUPeepholeOpt(*TM));
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addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
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// This callbacks this pass uses are not implemented yet on SI.
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addPass(createAMDGPUIndirectAddressingPass(*TM));
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}
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return false;
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}
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bool AMDGPUPassConfig::addPreRegAlloc() {
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
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addPass(createSIAssignInterpRegsPass(*TM));
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}
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addPass(createAMDGPUConvertToISAPass(*TM));
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return false;
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}
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bool AMDGPUPassConfig::addPostRegAlloc() {
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
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addPass(createSIInsertWaits(*TM));
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}
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return false;
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}
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bool AMDGPUPassConfig::addPreSched2() {
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addPass(&IfConverterID);
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return false;
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}
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bool AMDGPUPassConfig::addPreEmitPass() {
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const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
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if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
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addPass(createAMDGPUCFGPreparationPass(*TM));
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addPass(createAMDGPUCFGStructurizerPass(*TM));
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addPass(createR600ExpandSpecialInstrsPass(*TM));
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addPass(&FinalizeMachineBundlesID);
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} else {
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addPass(createSILowerControlFlowPass(*TM));
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}
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return false;
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}
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