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A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
153 lines
5.0 KiB
C++
153 lines
5.0 KiB
C++
//===-- SIAssignInterpRegs.cpp - Assign interpolation registers -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This pass maps the pseudo interpolation registers to the correct physical
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/// registers.
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//
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/// Prior to executing a fragment shader, the GPU loads interpolation
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/// parameters into physical registers. The specific physical register that each
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/// interpolation parameter ends up in depends on the type of the interpolation
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/// parameter as well as how many interpolation parameters are used by the
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/// shader.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDIL.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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namespace {
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class SIAssignInterpRegsPass : public MachineFunctionPass {
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private:
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static char ID;
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TargetMachine &TM;
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void addLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
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unsigned physReg, unsigned virtReg);
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public:
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SIAssignInterpRegsPass(TargetMachine &tm) :
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MachineFunctionPass(ID), TM(tm) { }
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const { return "SI Assign intrpolation registers"; }
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};
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} // End anonymous namespace
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char SIAssignInterpRegsPass::ID = 0;
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#define INTERP_VALUES 16
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#define REQUIRED_VALUE_MAX_INDEX 7
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struct InterpInfo {
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bool Enabled;
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unsigned Regs[3];
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unsigned RegCount;
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};
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FunctionPass *llvm::createSIAssignInterpRegsPass(TargetMachine &tm) {
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return new SIAssignInterpRegsPass(tm);
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}
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bool SIAssignInterpRegsPass::runOnMachineFunction(MachineFunction &MF) {
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struct InterpInfo InterpUse[INTERP_VALUES] = {
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{false, {AMDGPU::PERSP_SAMPLE_I, AMDGPU::PERSP_SAMPLE_J}, 2},
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{false, {AMDGPU::PERSP_CENTER_I, AMDGPU::PERSP_CENTER_J}, 2},
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{false, {AMDGPU::PERSP_CENTROID_I, AMDGPU::PERSP_CENTROID_J}, 2},
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{false, {AMDGPU::PERSP_I_W, AMDGPU::PERSP_J_W, AMDGPU::PERSP_1_W}, 3},
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{false, {AMDGPU::LINEAR_SAMPLE_I, AMDGPU::LINEAR_SAMPLE_J}, 2},
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{false, {AMDGPU::LINEAR_CENTER_I, AMDGPU::LINEAR_CENTER_J}, 2},
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{false, {AMDGPU::LINEAR_CENTROID_I, AMDGPU::LINEAR_CENTROID_J}, 2},
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{false, {AMDGPU::LINE_STIPPLE_TEX_COORD}, 1},
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{false, {AMDGPU::POS_X_FLOAT}, 1},
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{false, {AMDGPU::POS_Y_FLOAT}, 1},
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{false, {AMDGPU::POS_Z_FLOAT}, 1},
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{false, {AMDGPU::POS_W_FLOAT}, 1},
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{false, {AMDGPU::FRONT_FACE}, 1},
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{false, {AMDGPU::ANCILLARY}, 1},
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{false, {AMDGPU::SAMPLE_COVERAGE}, 1},
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{false, {AMDGPU::POS_FIXED_PT}, 1}
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};
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SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();
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// This pass is only needed for pixel shaders.
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if (MFI->ShaderType != ShaderType::PIXEL) {
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return false;
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}
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MachineRegisterInfo &MRI = MF.getRegInfo();
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bool ForceEnable = true;
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// First pass, mark the interpolation values that are used.
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for (unsigned InterpIdx = 0; InterpIdx < INTERP_VALUES; InterpIdx++) {
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for (unsigned RegIdx = 0; RegIdx < InterpUse[InterpIdx].RegCount;
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RegIdx++) {
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InterpUse[InterpIdx].Enabled = InterpUse[InterpIdx].Enabled ||
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!MRI.use_empty(InterpUse[InterpIdx].Regs[RegIdx]);
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if (InterpUse[InterpIdx].Enabled &&
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InterpIdx <= REQUIRED_VALUE_MAX_INDEX) {
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ForceEnable = false;
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}
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}
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}
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// At least one interpolation mode must be enabled or else the GPU will hang.
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if (ForceEnable) {
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InterpUse[0].Enabled = true;
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}
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unsigned UsedVgprs = 0;
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// Second pass, replace with VGPRs.
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for (unsigned InterpIdx = 0; InterpIdx < INTERP_VALUES; InterpIdx++) {
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if (!InterpUse[InterpIdx].Enabled) {
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continue;
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}
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MFI->SPIPSInputAddr |= (1 << InterpIdx);
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for (unsigned RegIdx = 0; RegIdx < InterpUse[InterpIdx].RegCount;
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RegIdx++, UsedVgprs++) {
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unsigned NewReg = AMDGPU::VReg_32RegClass.getRegister(UsedVgprs);
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unsigned VirtReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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MRI.replaceRegWith(InterpUse[InterpIdx].Regs[RegIdx], VirtReg);
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addLiveIn(&MF, MRI, NewReg, VirtReg);
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}
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}
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return false;
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}
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void SIAssignInterpRegsPass::addLiveIn(MachineFunction * MF,
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MachineRegisterInfo & MRI,
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unsigned physReg, unsigned virtReg) {
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const TargetInstrInfo * TII = TM.getInstrInfo();
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if (!MRI.isLiveIn(physReg)) {
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MRI.addLiveIn(physReg, virtReg);
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MF->front().addLiveIn(physReg);
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BuildMI(MF->front(), MF->front().begin(), DebugLoc(),
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TII->get(TargetOpcode::COPY), virtReg)
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.addReg(physReg);
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} else {
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MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg));
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}
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}
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