Chandler Carruth c3d7858505 [x86] Simplify the pre-SSSE3 v16i8 lowering significantly by decomposing ... them into permutes and a blend with the generic decomposition logic. This works really well in almost every case and lets the code only manage the expansion of a single input into two v8i16 vectors to perform the actual shuffle. The blend-based merging is often much nicer than the pack based merging that this replaces. The only place where it isn't we end up blending between two packs when we could do a single pack. To handle that case, just teach the v2i64 lowering to handle these blends by digging out the operands. With this we're down to only really random permutations that cause an explosion of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229849 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-19 13:15:12 +00:00
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AArch64	AArch64: Safely handle the incoming sret call argument.	2015-02-16 18:10:47 +00:00
ARM	llvm-mc: Use Target::createNullStreamer to fix crashes on target-specific asm directives.	2015-02-19 00:45:04 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips	[mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generator	2015-02-19 11:51:32 +00:00
MSP430
NVPTX
PowerPC	This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions.	2015-02-18 16:21:46 +00:00
R600	R600/SI: Add missing offset operand to buffer bothen	2015-02-18 02:04:38 +00:00
SPARC	SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too	2015-02-16 21:47:58 +00:00
SystemZ	[SystemZ] Support all TLS access models - CodeGen part	2015-02-18 09:13:27 +00:00
Thumb
Thumb2
X86	[x86] Simplify the pre-SSSE3 v16i8 lowering significantly by decomposing	2015-02-19 13:15:12 +00:00
XCore