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https://github.com/c64scene-ar/llvm-6502.git
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67a2b82b14
Register coalescing can change the target of a RegPair hint to a physreg, we should not crash on this. This also slightly improved the way ARMBaseRegisterInfo::updateRegAllocHint() works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233987 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
757 B
LLVM
23 lines
757 B
LLVM
; RUN: llc -o - %s
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; ARM target used to fail an assertion if RegPair{Odd|Even} hint pointed to a
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; physreg.
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target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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target triple = "thumbv7-apple-tvos8.3.0"
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declare i8* @llvm.frameaddress(i32) #1
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declare i8* @llvm.returnaddress(i32) #1
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@somevar = global [2 x i32] [i32 0, i32 0]
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define void @__ubsan_handle_shift_out_of_bounds() #0 {
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entry:
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%0 = tail call i8* @llvm.frameaddress(i32 0)
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%1 = ptrtoint i8* %0 to i32
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%2 = tail call i8* @llvm.returnaddress(i32 0)
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%3 = ptrtoint i8* %2 to i32
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%val0 = insertvalue [2 x i32] [i32 undef, i32 undef], i32 %3, 0
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%val1 = insertvalue [2 x i32] %val0, i32 %1, 1
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store [2 x i32] %val1, [2 x i32]* @somevar, align 8
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ret void
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}
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