mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-08 03:29:18 +00:00
184f8f7c10
TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
76 lines
1.5 KiB
LLVM
76 lines
1.5 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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; zext
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define i32 @zext_8_32(i8 %a) nounwind ssp {
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; ELF64: zext_8_32
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%r = zext i8 %a to i32
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; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
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ret i32 %r
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}
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define i32 @zext_16_32(i16 %a) nounwind ssp {
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; ELF64: zext_16_32
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%r = zext i16 %a to i32
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; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
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ret i32 %r
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}
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define i64 @zext_8_64(i8 %a) nounwind ssp {
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; ELF64: zext_8_64
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%r = zext i8 %a to i64
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
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ret i64 %r
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}
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define i64 @zext_16_64(i16 %a) nounwind ssp {
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; ELF64: zext_16_64
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%r = zext i16 %a to i64
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
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ret i64 %r
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}
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define i64 @zext_32_64(i32 %a) nounwind ssp {
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; ELF64: zext_32_64
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%r = zext i32 %a to i64
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
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ret i64 %r
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}
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; sext
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define i32 @sext_8_32(i8 %a) nounwind ssp {
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; ELF64: sext_8_32
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%r = sext i8 %a to i32
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; ELF64: extsb
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ret i32 %r
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}
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define i32 @sext_16_32(i16 %a) nounwind ssp {
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; ELF64: sext_16_32
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%r = sext i16 %a to i32
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; ELF64: extsh
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ret i32 %r
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}
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define i64 @sext_8_64(i8 %a) nounwind ssp {
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; ELF64: sext_8_64
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%r = sext i8 %a to i64
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; ELF64: extsb
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ret i64 %r
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}
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define i64 @sext_16_64(i16 %a) nounwind ssp {
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; ELF64: sext_16_64
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%r = sext i16 %a to i64
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; ELF64: extsh
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ret i64 %r
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}
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define i64 @sext_32_64(i32 %a) nounwind ssp {
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; ELF64: sext_32_64
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%r = sext i32 %a to i64
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; ELF64: extsw
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ret i64 %r
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}
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