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https://github.com/c64scene-ar/llvm-6502.git
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10ae865847
The old target DAG combine that allowed for performing int_to_fp(fp_to_int(x)) without a load/store pair is updated here with support for unsigned integers, and to support single-precision values without a third rounding step, on newer cores with the appropriate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225248 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
1.5 KiB
LLVM
71 lines
1.5 KiB
LLVM
; RUN: llc -mcpu=a2 < %s | FileCheck %s -check-prefix=FPCVT
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; RUN: llc -mcpu=ppc64 < %s | FileCheck %s -check-prefix=PPC64
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind readnone
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define float @fool(float %X) #0 {
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entry:
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%conv = fptosi float %X to i64
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%conv1 = sitofp i64 %conv to float
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ret float %conv1
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; FPCVT-LABEL: @fool
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; FPCVT: fctidz [[REG1:[0-9]+]], 1
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; FPCVT: fcfids 1, [[REG1]]
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; FPCVT: blr
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; PPC64-LABEL: @fool
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; PPC64: fctidz [[REG1:[0-9]+]], 1
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; PPC64: fcfid [[REG2:[0-9]+]], [[REG1]]
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; PPC64: frsp 1, [[REG2]]
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; PPC64: blr
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}
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; Function Attrs: nounwind readnone
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define double @foodl(double %X) #0 {
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entry:
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%conv = fptosi double %X to i64
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%conv1 = sitofp i64 %conv to double
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ret double %conv1
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; FPCVT-LABEL: @foodl
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; FPCVT: fctidz [[REG1:[0-9]+]], 1
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; FPCVT: fcfid 1, [[REG1]]
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; FPCVT: blr
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; PPC64-LABEL: @foodl
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; PPC64: fctidz [[REG1:[0-9]+]], 1
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; PPC64: fcfid 1, [[REG1]]
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; PPC64: blr
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}
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; Function Attrs: nounwind readnone
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define float @fooul(float %X) #0 {
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entry:
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%conv = fptoui float %X to i64
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%conv1 = uitofp i64 %conv to float
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ret float %conv1
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; FPCVT-LABEL: @fooul
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; FPCVT: fctiduz [[REG1:[0-9]+]], 1
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; FPCVT: fcfidus 1, [[REG1]]
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; FPCVT: blr
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}
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; Function Attrs: nounwind readnone
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define double @fooudl(double %X) #0 {
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entry:
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%conv = fptoui double %X to i64
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%conv1 = uitofp i64 %conv to double
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ret double %conv1
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; FPCVT-LABEL: @fooudl
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; FPCVT: fctiduz [[REG1:[0-9]+]], 1
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; FPCVT: fcfidu 1, [[REG1]]
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; FPCVT: blr
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}
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attributes #0 = { nounwind readnone }
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