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101025c33d
Patch by Bill Seurer; committed on his behalf. These test cases generate slightly different code sequences when VSX is activated and thus fail. The update turns off VSX explicitly for the existing checks and then adds a second set of checks for most of them that test the VSX instruction output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220019 91177308-0d34-0410-b5e6-96231b3b80d8
181 lines
4.4 KiB
LLVM
181 lines
4.4 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx | FileCheck -check-prefix=CHECK-FM %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-FM-VSX %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define double @zerocmp1(double %a, double %y, double %z) #0 {
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entry:
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%cmp = fcmp ult double %a, 0.000000e+00
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%z.y = select i1 %cmp, double %z, double %y
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ret double %z.y
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; CHECK: @zerocmp1
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; CHECK-NOT: fsel
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; CHECK: blr
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; CHECK-FM: @zerocmp1
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; CHECK-FM: fsel 1, 1, 2, 3
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; CHECK-FM: blr
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; CHECK-FM-VSX: @zerocmp1
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; CHECK-FM-VSX: fsel 1, 1, 2, 3
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; CHECK-FM-VSX: blr
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}
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define double @zerocmp2(double %a, double %y, double %z) #0 {
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entry:
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%cmp = fcmp ogt double %a, 0.000000e+00
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%y.z = select i1 %cmp, double %y, double %z
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ret double %y.z
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; CHECK: @zerocmp2
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; CHECK-NOT: fsel
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; CHECK: blr
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; CHECK-FM: @zerocmp2
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; CHECK-FM: fneg [[REG:[0-9]+]], 1
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; CHECK-FM: fsel 1, [[REG]], 3, 2
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; CHECK-FM: blr
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; CHECK-FM-VSX: @zerocmp2
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; CHECK-FM-VSX: xsnegdp [[REG:[0-9]+]], 1
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; CHECK-FM-VSX: fsel 1, [[REG]], 3, 2
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; CHECK-FM-VSX: blr
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}
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define double @zerocmp3(double %a, double %y, double %z) #0 {
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entry:
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%cmp = fcmp oeq double %a, 0.000000e+00
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%y.z = select i1 %cmp, double %y, double %z
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ret double %y.z
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; CHECK: @zerocmp3
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; CHECK-NOT: fsel
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; CHECK: blr
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; CHECK-FM: @zerocmp3
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; CHECK-FM: fsel [[REG:[0-9]+]], 1, 2, 3
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; CHECK-FM: fneg [[REG2:[0-9]+]], 1
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; CHECK-FM: fsel 1, [[REG2]], [[REG]], 3
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; CHECK-FM: blr
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; CHECK-FM-VSX: @zerocmp3
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; CHECK-FM-VSX: xsnegdp [[REG2:[0-9]+]], 1
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; CHECK-FM-VSX: fsel [[REG:[0-9]+]], 1, 2, 3
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; CHECK-FM-VSX: fsel 1, [[REG2]], [[REG]], 3
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; CHECK-FM-VSX: blr
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}
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define double @min1(double %a, double %b) #0 {
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entry:
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%cmp = fcmp ole double %a, %b
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%cond = select i1 %cmp, double %a, double %b
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ret double %cond
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; CHECK: @min1
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; CHECK-NOT: fsel
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; CHECK: blr
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; CHECK-FM: @min1
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; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
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; CHECK-FM: fsel 1, [[REG]], 1, 2
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; CHECK-FM: blr
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; CHECK-FM-VSX: @min1
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; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
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; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
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; CHECK-FM-VSX: blr
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}
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define double @max1(double %a, double %b) #0 {
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entry:
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%cmp = fcmp oge double %a, %b
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%cond = select i1 %cmp, double %a, double %b
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ret double %cond
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; CHECK: @max1
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; CHECK-NOT: fsel
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; CHECK: blr
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; CHECK-FM: @max1
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; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
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; CHECK-FM: fsel 1, [[REG]], 1, 2
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; CHECK-FM: blr
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; CHECK-FM-VSX: @max1
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; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
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; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
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; CHECK-FM-VSX: blr
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}
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define double @cmp1(double %a, double %b, double %y, double %z) #0 {
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entry:
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%cmp = fcmp ult double %a, %b
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%z.y = select i1 %cmp, double %z, double %y
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ret double %z.y
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; CHECK: @cmp1
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; CHECK-NOT: fsel
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; CHECK: blr
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; CHECK-FM: @cmp1
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; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
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; CHECK-FM: fsel 1, [[REG]], 3, 4
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; CHECK-FM: blr
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; CHECK-FM-VSX: @cmp1
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; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
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; CHECK-FM-VSX: fsel 1, [[REG]], 3, 4
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; CHECK-FM-VSX: blr
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}
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define double @cmp2(double %a, double %b, double %y, double %z) #0 {
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entry:
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%cmp = fcmp ogt double %a, %b
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%y.z = select i1 %cmp, double %y, double %z
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ret double %y.z
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; CHECK: @cmp2
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; CHECK-NOT: fsel
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; CHECK: blr
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; CHECK-FM: @cmp2
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; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
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; CHECK-FM: fsel 1, [[REG]], 4, 3
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; CHECK-FM: blr
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; CHECK-FM-VSX: @cmp2
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; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
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; CHECK-FM-VSX: fsel 1, [[REG]], 4, 3
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; CHECK-FM-VSX: blr
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}
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define double @cmp3(double %a, double %b, double %y, double %z) #0 {
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entry:
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%cmp = fcmp oeq double %a, %b
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%y.z = select i1 %cmp, double %y, double %z
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ret double %y.z
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; CHECK: @cmp3
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; CHECK-NOT: fsel
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; CHECK: blr
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; CHECK-FM: @cmp3
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; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
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; CHECK-FM: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
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; CHECK-FM: fneg [[REG3:[0-9]+]], [[REG]]
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; CHECK-FM: fsel 1, [[REG3]], [[REG2]], 4
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; CHECK-FM: blr
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; CHECK-FM-VSX: @cmp3
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; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
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; CHECK-FM-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]]
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; CHECK-FM-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
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; CHECK-FM-VSX: fsel 1, [[REG3]], [[REG2]], 4
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; CHECK-FM-VSX: blr
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}
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attributes #0 = { nounwind readnone }
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