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f45717e985
The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
16 lines
369 B
LLVM
16 lines
369 B
LLVM
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; RUN: llc < %s | FileCheck %s
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define i64 @test1() nounwind {
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entry:
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%r = call i64 @llvm.readcyclecounter()
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ret i64 %r
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}
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; CHECK: @test1
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; CHECK: mfspr 3, 268
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declare i64 @llvm.readcyclecounter()
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