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184f8f7c10
TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
40 lines
1.3 KiB
LLVM
40 lines
1.3 KiB
LLVM
; RUN: llc < %s -march=ppc32 | grep rotlwi | count 2
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; RUN: llc < %s -march=ppc32 | grep clrlwi | count 2
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; RUN: llc < %s -march=ppc32 | grep rotlw | count 4
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; RUN: llc < %s -march=ppc32 | not grep or
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define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
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%shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
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%B = shl i32 %A, %shift.upgrd.1 ; <i32> [#uses=1]
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%Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
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%shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
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%C = lshr i32 %A, %shift.upgrd.2 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
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%shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
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%B = lshr i32 %A, %shift.upgrd.3 ; <i32> [#uses=1]
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%Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
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%shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
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%C = shl i32 %A, %shift.upgrd.4 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i32 @rotli32(i32 %A) nounwind {
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%B = shl i32 %A, 5 ; <i32> [#uses=1]
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%C = lshr i32 %A, 27 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i32 @rotri32(i32 %A) nounwind {
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%B = lshr i32 %A, 5 ; <i32> [#uses=1]
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%C = shl i32 %A, 27 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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