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https://github.com/c64scene-ar/llvm-6502.git
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63292d1bba
My recent patch to add support for ISA 2.07 vector pack/unpack instructions didn't properly check for availability of the vpkudum instruction when recognizing it as a special vector shuffle case. This causes us to leave the vector shuffle in place (rather than converting it to a vector permute) so that it can be recognized later as a vpkudum, but that pattern is invalid for processors prior to POWER8. Thus LLVM crashes with an "unable to select" message. We observed this since one of our buildbots is configured to generate code for a POWER7. This patch fixes the problem by checking for availability of the vpkudum instruction during custom lowering of vector shuffles. I've added a test case variant for the vpkudum pattern when the instruction isn't available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237952 91177308-0d34-0410-b5e6-96231b3b80d8
55 lines
2.0 KiB
LLVM
55 lines
2.0 KiB
LLVM
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck -check-prefix=CHECK-PWR7 %s
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define void @VPKUDUM_unary(<2 x i64>* %A) {
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entry:
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%tmp = load <2 x i64>, <2 x i64>* %A
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%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
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%tmp3 = extractelement <4 x i32> %tmp2, i32 1
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%tmp4 = extractelement <4 x i32> %tmp2, i32 3
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%tmp5 = insertelement <4 x i32> undef, i32 %tmp3, i32 0
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%tmp6 = insertelement <4 x i32> %tmp5, i32 %tmp4, i32 1
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%tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 2
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%tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 3
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%tmp9 = bitcast <4 x i32> %tmp8 to <2 x i64>
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store <2 x i64> %tmp9, <2 x i64>* %A
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ret void
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}
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; CHECK-LABEL: @VPKUDUM_unary
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; CHECK-NOT: vperm
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; CHECK-NOT: vmrglw
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; CHECK-NOT: vmrghw
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; CHECK: vpkudum
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; CHECK-PWR7: vmrglw
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; CHECK-PWR7: vmrghw
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; CHECK-PWR7: vmrglw
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define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) {
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entry:
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%tmp = load <2 x i64>, <2 x i64>* %A
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%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
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%tmp3 = load <2 x i64>, <2 x i64>* %B
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%tmp4 = bitcast <2 x i64> %tmp3 to <4 x i32>
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%tmp5 = extractelement <4 x i32> %tmp2, i32 1
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%tmp6 = extractelement <4 x i32> %tmp2, i32 3
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%tmp7 = extractelement <4 x i32> %tmp4, i32 1
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%tmp8 = extractelement <4 x i32> %tmp4, i32 3
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%tmp9 = insertelement <4 x i32> undef, i32 %tmp5, i32 0
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%tmp10 = insertelement <4 x i32> %tmp9, i32 %tmp6, i32 1
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%tmp11 = insertelement <4 x i32> %tmp10, i32 %tmp7, i32 2
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%tmp12 = insertelement <4 x i32> %tmp11, i32 %tmp8, i32 3
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%tmp13 = bitcast <4 x i32> %tmp12 to <2 x i64>
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store <2 x i64> %tmp13, <2 x i64>* %A
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ret void
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}
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; CHECK-LABEL: @VPKUDUM
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; CHECK-NOT: vperm
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; CHECK-NOT: vmrglw
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; CHECK-NOT: vmrghw
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; CHECK: vpkudum
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; CHECK-PWR7: vmrglw
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; CHECK-PWR7: vmrghw
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; CHECK-PWR7: vmrglw
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