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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
1.4 KiB
LLVM
56 lines
1.4 KiB
LLVM
; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck %s
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; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck -check-prefix=CHECK-REG %s
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; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck %s
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; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Unaligned loads/stores on P8 and later should use VSX where possible.
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define <2 x double> @test28u(<2 x double>* %a) {
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%v = load <2 x double>, <2 x double>* %a, align 8
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ret <2 x double> %v
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; CHECK-LABEL: @test28u
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; CHECK: lxvd2x 34, 0, 3
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; CHECK: blr
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}
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define void @test29u(<2 x double>* %a, <2 x double> %b) {
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store <2 x double> %b, <2 x double>* %a, align 8
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ret void
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; CHECK-LABEL: @test29u
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; CHECK: stxvd2x 34, 0, 3
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; CHECK: blr
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}
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define <4 x float> @test32u(<4 x float>* %a) {
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%v = load <4 x float>, <4 x float>* %a, align 8
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ret <4 x float> %v
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; CHECK-REG-LABEL: @test32u
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; CHECK-REG: lxvw4x 34, 0, 3
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test32u
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; CHECK-FISL: lxvw4x 0, 0, 3
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; CHECK-FISL: xxlor 34, 0, 0
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; CHECK-FISL: blr
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}
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define void @test33u(<4 x float>* %a, <4 x float> %b) {
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store <4 x float> %b, <4 x float>* %a, align 8
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ret void
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; CHECK-REG-LABEL: @test33u
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; CHECK-REG: stxvw4x 34, 0, 3
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; CHECK-REG: blr
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; CHECK-FISL-LABEL: @test33u
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; CHECK-FISL: vor 3, 2, 2
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; CHECK-FISL: stxvw4x 35, 0, 3
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; CHECK-FISL: blr
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}
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