mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-08 18:30:04 +00:00
aedb288d86
One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196906 91177308-0d34-0410-b5e6-96231b3b80d8
13 lines
281 B
LLVM
13 lines
281 B
LLVM
; Test 16-bit atomic stores.
|
|
;
|
|
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
|
|
|
define void @f1(i16 %val, i16 *%src) {
|
|
; CHECK-LABEL: f1:
|
|
; CHECK: sth %r2, 0(%r3)
|
|
; CHECK: bcr 1{{[45]}}, %r0
|
|
; CHECK: br %r14
|
|
store atomic i16 %val, i16 *%src seq_cst, align 2
|
|
ret void
|
|
}
|