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cf0fa9b9dd
The z13 vector facility includes some instructions that operate only on the high f64 in a v2f64, effectively extending the FP register set from 16 to 32 registers. It's still better to use the old instructions if the operands happen to fit though, since the older instructions have a shorter encoding. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236524 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
1.6 KiB
LLVM
61 lines
1.6 KiB
LLVM
; Test vector addition.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a v16i8 addition.
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define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vab %v24, %v26, %v28
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; CHECK: br %r14
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%ret = add <16 x i8> %val1, %val2
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ret <16 x i8> %ret
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}
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; Test a v8i16 addition.
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define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: vah %v24, %v26, %v28
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; CHECK: br %r14
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%ret = add <8 x i16> %val1, %val2
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ret <8 x i16> %ret
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}
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; Test a v4i32 addition.
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define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: vaf %v24, %v26, %v28
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; CHECK: br %r14
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%ret = add <4 x i32> %val1, %val2
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ret <4 x i32> %ret
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}
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; Test a v2i64 addition.
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define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f4:
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; CHECK: vag %v24, %v26, %v28
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; CHECK: br %r14
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%ret = add <2 x i64> %val1, %val2
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ret <2 x i64> %ret
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}
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; Test a v2f64 addition.
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define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1,
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<2 x double> %val2) {
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; CHECK-LABEL: f5:
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; CHECK: vfadb %v24, %v26, %v28
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; CHECK: br %r14
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%ret = fadd <2 x double> %val1, %val2
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ret <2 x double> %ret
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}
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; Test an f64 addition that uses vector registers.
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define double @f6(<2 x double> %val1, <2 x double> %val2) {
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; CHECK-LABEL: f6:
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; CHECK: wfadb %f0, %v24, %v26
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; CHECK: br %r14
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%scalar1 = extractelement <2 x double> %val1, i32 0
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%scalar2 = extractelement <2 x double> %val2, i32 0
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%ret = fadd double %scalar1, %scalar2
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ret double %ret
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}
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