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1bd30dce7b
Silvermont can only decode one instruction per cycle if the instruction exceeds 8 bytes. Also in Silvermont instructions with more than 3 prefixes will cause 3 cycle penalty. Maximum nop length is limited to 7 bytes when used for padding on Silvermont. For other x86 processors max nop length remains unchanged 15 bytes. Differential Revision: http://reviews.llvm.org/D4374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212321 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
1.1 KiB
ArmAsm
26 lines
1.1 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
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# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
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# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
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# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
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# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=SLM %s
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# Ensure alignment directives also emit sequences of 15-byte NOPs on processors
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# capable of using long NOPs.
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inc %eax
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.p2align 5
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inc %eax
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# CHECK: 0: inc
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# CHECK-NEXT: 1: nop
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# CHECK-NEXT: 10: nop
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# CHECK-NEXT: 1f: nop
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# CHECK-NEXT: 20: inc
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# On Silvermont we emit only 7 byte NOPs since longer NOPs are not profitable
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# SLM: 0: inc
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# SLM-NEXT: 1: nop
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# SLM-NEXT: 8: nop
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# SLM-NEXT: f: nop
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# SLM-NEXT: 16: nop
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# SLM-NEXT: 1d: nop
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# SLM-NEXT: 20: inc
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