mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-22 07:32:48 +00:00
3575222175
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166566 91177308-0d34-0410-b5e6-96231b3b80d8
94 lines
3.7 KiB
LLVM
94 lines
3.7 KiB
LLVM
; RUN: llc < %s -mtriple=i386-pc-win32 -mcpu=nehalem | FileCheck -check-prefix=WIN32 %s
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; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=nehalem | FileCheck -check-prefix=WIN64 %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=nehalem | FileCheck -check-prefix=NOT_WIN %s
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declare <16 x float> @func_float16_ptr(<16 x float>, <16 x float> *)
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declare <16 x float> @func_float16(<16 x float>, <16 x float>)
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; WIN64: testf16_inp
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; WIN64: addps {{.*}}, {{%xmm[0-3]}}
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; WIN64: addps {{.*}}, {{%xmm[0-3]}}
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; WIN64: addps {{.*}}, {{%xmm[0-3]}}
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; WIN64: addps {{.*}}, {{%xmm[0-3]}}
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; WIN64: leaq {{.*}}(%rsp), %rcx
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; WIN64: call
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; WIN64: ret
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; WIN32: testf16_inp
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; WIN32: movl %eax, (%esp)
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; WIN32: addps {{.*}}, {{%xmm[0-3]}}
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; WIN32: addps {{.*}}, {{%xmm[0-3]}}
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; WIN32: addps {{.*}}, {{%xmm[0-3]}}
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; WIN32: addps {{.*}}, {{%xmm[0-3]}}
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; WIN32: call
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; WIN32: ret
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; NOT_WIN: testf16_inp
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; NOT_WIN: addps {{.*}}, {{%xmm[0-3]}}
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; NOT_WIN: addps {{.*}}, {{%xmm[0-3]}}
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; NOT_WIN: addps {{.*}}, {{%xmm[0-3]}}
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; NOT_WIN: addps {{.*}}, {{%xmm[0-3]}}
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; NOT_WIN: leaq {{.*}}(%rsp), %rdi
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; NOT_WIN: call
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; NOT_WIN: ret
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;test calling conventions - input parameters
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define <16 x float> @testf16_inp(<16 x float> %a, <16 x float> %b) nounwind {
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%y = alloca <16 x float>, align 16
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%x = fadd <16 x float> %a, %b
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%1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)
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%2 = load <16 x float>* %y, align 16
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%3 = fadd <16 x float> %2, %1
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ret <16 x float> %3
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}
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;test calling conventions - preserved registers
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; preserved xmm6-xmm15
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; WIN64: testf16_regs
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; WIN64: call
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; WIN64: addps {{%xmm[6-9]}}, {{.*}}
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; WIN64: addps {{%xmm[6-9]}}, {{.*}}
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; WIN64: ret
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; preserved xmm8-xmm15
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; NOT_WIN: testf16_regs
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; NOT_WIN: call
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; NOT_WIN: addps {{%xmm([8-9]|1[0-1])}}, {{.*}}
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; NOT_WIN: addps {{%xmm([8-9]|1[0-1])}}, {{.*}}
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; NOT_WIN: addps {{%xmm([8-9]|1[0-1])}}, {{.*}}
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; NOT_WIN: addps {{%xmm([8-9]|1[0-1])}}, {{.*}}
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; NOT_WIN: ret
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define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind {
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%y = alloca <16 x float>, align 16
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%x = fadd <16 x float> %a, %b
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%1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)
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%2 = load <16 x float>* %y, align 16
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%3 = fadd <16 x float> %1, %b
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%4 = fadd <16 x float> %2, %3
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ret <16 x float> %4
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}
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; test calling conventions - prolog and epilog
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; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
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; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
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; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
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; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
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; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
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; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
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; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
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; NOT_WIN: movaps {{%xmm([8-9]|1[0-5])}}, {{.*(%rsp).*}} ## 16-byte Spill
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; NOT_WIN: call
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; NOT_WIN: movaps {{.*(%rsp).*}}, {{%xmm([8-9]|1[0-5])}} ## 16-byte Reload
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; NOT_WIN: movaps {{.*(%rsp).*}}, {{%xmm([8-9]|1[0-5])}} ## 16-byte Reload
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; NOT_WIN: movaps {{.*(%rsp).*}}, {{%xmm([8-9]|1[0-5])}} ## 16-byte Reload
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; NOT_WIN: movaps {{.*(%rsp).*}}, {{%xmm([8-9]|1[0-5])}} ## 16-byte Reload
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; NOT_WIN: movaps {{.*(%rsp).*}}, {{%xmm([8-9]|1[0-5])}} ## 16-byte Reload
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; NOT_WIN: movaps {{.*(%rsp).*}}, {{%xmm([8-9]|1[0-5])}} ## 16-byte Reload
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; NOT_WIN: movaps {{.*(%rsp).*}}, {{%xmm([8-9]|1[0-5])}} ## 16-byte Reload
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; NOT_WIN: movaps {{.*(%rsp).*}}, {{%xmm([8-9]|1[0-5])}} ## 16-byte Reload
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define intel_ocl_bicc <16 x float> @test_prolog_epilog(<16 x float> %a, <16 x float> %b) nounwind {
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%c = call <16 x float> @func_float16(<16 x float> %a, <16 x float> %b)
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ret <16 x float> %c
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}
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