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If we create new intervals for a variable that is being spilled, then those new intervals are not guaranteed to also spill. This means that anything reading from the original spilling value might not get the correct value if spills were missed. Fixes <rdar://problem/10546864> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146428 91177308-0d34-0410-b5e6-96231b3b80d8
212 lines
8.4 KiB
C++
212 lines
8.4 KiB
C++
//===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The LiveRangeEdit class represents changes done to a virtual register when it
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// is spilled or split.
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//
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// The parent register is never changed. Instead, a number of new virtual
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// registers are created and added to the newRegs vector.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
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#define LLVM_CODEGEN_LIVERANGEEDIT_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/CodeGen/LiveInterval.h"
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namespace llvm {
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class AliasAnalysis;
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class LiveIntervals;
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class MachineLoopInfo;
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class MachineRegisterInfo;
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class VirtRegMap;
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class LiveRangeEdit {
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public:
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/// Callback methods for LiveRangeEdit owners.
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struct Delegate {
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/// Called immediately before erasing a dead machine instruction.
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virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
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/// Called when a virtual register is no longer used. Return false to defer
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/// its deletion from LiveIntervals.
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virtual bool LRE_CanEraseVirtReg(unsigned) { return true; }
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/// Called before shrinking the live range of a virtual register.
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virtual void LRE_WillShrinkVirtReg(unsigned) {}
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/// Called after cloning a virtual register.
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/// This is used for new registers representing connected components of Old.
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virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {}
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virtual ~Delegate() {}
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};
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private:
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LiveInterval &parent_;
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SmallVectorImpl<LiveInterval*> &newRegs_;
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Delegate *const delegate_;
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const SmallVectorImpl<LiveInterval*> *uselessRegs_;
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/// firstNew_ - Index of the first register added to newRegs_.
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const unsigned firstNew_;
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/// scannedRemattable_ - true when remattable values have been identified.
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bool scannedRemattable_;
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/// remattable_ - Values defined by remattable instructions as identified by
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/// tii.isTriviallyReMaterializable().
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SmallPtrSet<const VNInfo*,4> remattable_;
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/// rematted_ - Values that were actually rematted, and so need to have their
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/// live range trimmed or entirely removed.
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SmallPtrSet<const VNInfo*,4> rematted_;
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/// scanRemattable - Identify the parent_ values that may rematerialize.
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void scanRemattable(LiveIntervals &lis,
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const TargetInstrInfo &tii,
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AliasAnalysis *aa);
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// OrigIdx are also available with the same value at UseIdx.
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bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
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SlotIndex UseIdx, LiveIntervals &lis);
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/// foldAsLoad - If LI has a single use and a single def that can be folded as
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/// a load, eliminate the register by folding the def into the use.
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bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead,
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MachineRegisterInfo&, LiveIntervals&, const TargetInstrInfo&);
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public:
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/// Create a LiveRangeEdit for breaking down parent into smaller pieces.
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/// @param parent The register being spilled or split.
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/// @param newRegs List to receive any new registers created. This needn't be
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/// empty initially, any existing registers are ignored.
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/// @param uselessRegs List of registers that can't be used when
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/// rematerializing values because they are about to be removed.
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LiveRangeEdit(LiveInterval &parent,
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SmallVectorImpl<LiveInterval*> &newRegs,
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Delegate *delegate = 0,
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const SmallVectorImpl<LiveInterval*> *uselessRegs = 0)
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: parent_(parent), newRegs_(newRegs),
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delegate_(delegate),
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uselessRegs_(uselessRegs),
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firstNew_(newRegs.size()),
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scannedRemattable_(false) {}
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LiveInterval &getParent() const { return parent_; }
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unsigned getReg() const { return parent_.reg; }
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/// Iterator for accessing the new registers added by this edit.
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typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;
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iterator begin() const { return newRegs_.begin()+firstNew_; }
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iterator end() const { return newRegs_.end(); }
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unsigned size() const { return newRegs_.size()-firstNew_; }
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bool empty() const { return size() == 0; }
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LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; }
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ArrayRef<LiveInterval*> regs() const {
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return makeArrayRef(newRegs_).slice(firstNew_);
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}
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/// FIXME: Temporary accessors until we can get rid of
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/// LiveIntervals::AddIntervalsForSpills
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SmallVectorImpl<LiveInterval*> *getNewVRegs() { return &newRegs_; }
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const SmallVectorImpl<LiveInterval*> *getUselessVRegs() {
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return uselessRegs_;
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}
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/// createFrom - Create a new virtual register based on OldReg.
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LiveInterval &createFrom(unsigned OldReg, LiveIntervals&, VirtRegMap&);
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/// create - Create a new register with the same class and original slot as
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/// parent.
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LiveInterval &create(LiveIntervals &LIS, VirtRegMap &VRM) {
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return createFrom(getReg(), LIS, VRM);
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}
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/// anyRematerializable - Return true if any parent values may be
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/// rematerializable.
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/// This function must be called before any rematerialization is attempted.
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bool anyRematerializable(LiveIntervals&, const TargetInstrInfo&,
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AliasAnalysis*);
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/// checkRematerializable - Manually add VNI to the list of rematerializable
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/// values if DefMI may be rematerializable.
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bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
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const TargetInstrInfo&, AliasAnalysis*);
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/// Remat - Information needed to rematerialize at a specific location.
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struct Remat {
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VNInfo *ParentVNI; // parent_'s value at the remat location.
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MachineInstr *OrigMI; // Instruction defining ParentVNI.
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explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(0) {}
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};
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/// canRematerializeAt - Determine if ParentVNI can be rematerialized at
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/// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
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/// When cheapAsAMove is set, only cheap remats are allowed.
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bool canRematerializeAt(Remat &RM,
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SlotIndex UseIdx,
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bool cheapAsAMove,
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LiveIntervals &lis);
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/// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
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/// instruction into MBB before MI. The new instruction is mapped, but
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/// liveness is not updated.
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/// Return the SlotIndex of the new instruction.
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SlotIndex rematerializeAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg,
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const Remat &RM,
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LiveIntervals&,
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const TargetInstrInfo&,
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const TargetRegisterInfo&,
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bool Late = false);
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/// markRematerialized - explicitly mark a value as rematerialized after doing
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/// it manually.
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void markRematerialized(const VNInfo *ParentVNI) {
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rematted_.insert(ParentVNI);
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}
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/// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
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bool didRematerialize(const VNInfo *ParentVNI) const {
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return rematted_.count(ParentVNI);
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}
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/// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
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/// to erase it from LIS.
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void eraseVirtReg(unsigned Reg, LiveIntervals &LIS);
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/// eliminateDeadDefs - Try to delete machine instructions that are now dead
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/// (allDefsAreDead returns true). This may cause live intervals to be trimmed
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/// and further dead efs to be eliminated.
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/// RegsBeingSpilled lists registers currently being spilled by the register
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/// allocator. These registers should not be split into new intervals
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/// as currently those new intervals are not guaranteed to spill.
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void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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LiveIntervals&, VirtRegMap&,
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const TargetInstrInfo&,
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ArrayRef<unsigned> RegsBeingSpilled
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= ArrayRef<unsigned>());
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/// calculateRegClassAndHint - Recompute register class and hint for each new
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/// register.
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void calculateRegClassAndHint(MachineFunction&, LiveIntervals&,
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const MachineLoopInfo&);
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};
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}
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#endif
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