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https://github.com/c64scene-ar/llvm-6502.git
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b451f4e376
Thumb-1 only allows SP-based LDR and STR to be word-sized, and SP-base LDR, STR, and ADD only allow offsets that are a multiple of 4. Make some changes to better make use of these instructions: * Use word loads for anyext byte and halfword loads from the stack. * Enforce 4-byte alignment on objects accessed in this way, to ensure that the offset is valid. * Do the same for objects whose frame index is used, in order to avoid having to use more than one ADD to generate the frame index. * Correct how many bits of offset we think AddrModeT1_s has. Patch by John Brawn. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230496 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.4 KiB
LLVM
49 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=thumbv4t-none--eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V4T
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; RUN: llc -mtriple=thumbv6m-none--eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V6M
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; CHECK-LABEL: test1
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define i32 @test1(i32* %p) {
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; Offsets less than 8 can be generated in a single add
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; CHECK: adds [[NEWBASE:r[0-9]]], r0, #4
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%1 = getelementptr inbounds i32* %p, i32 1
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%2 = getelementptr inbounds i32* %p, i32 2
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%3 = getelementptr inbounds i32* %p, i32 3
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%4 = getelementptr inbounds i32* %p, i32 4
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; CHECK-NEXT: ldm [[NEWBASE]],
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%5 = load i32* %1, align 4
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%6 = load i32* %2, align 4
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%7 = load i32* %3, align 4
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%8 = load i32* %4, align 4
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%9 = add nsw i32 %5, %6
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%10 = add nsw i32 %9, %7
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%11 = add nsw i32 %10, %8
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ret i32 %11
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}
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; CHECK-LABEL: test2
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define i32 @test2(i32* %p) {
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; Offsets >=8 require a mov and an add
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; CHECK-V4T: movs [[NEWBASE:r[0-9]]], r0
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; CHECK-V6M: mov [[NEWBASE:r[0-9]]], r0
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; CHECK-NEXT: adds [[NEWBASE]], #8
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%1 = getelementptr inbounds i32* %p, i32 2
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%2 = getelementptr inbounds i32* %p, i32 3
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%3 = getelementptr inbounds i32* %p, i32 4
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%4 = getelementptr inbounds i32* %p, i32 5
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; CHECK-NEXT: ldm [[NEWBASE]],
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%5 = load i32* %1, align 4
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%6 = load i32* %2, align 4
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%7 = load i32* %3, align 4
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%8 = load i32* %4, align 4
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%9 = add nsw i32 %5, %6
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%10 = add nsw i32 %9, %7
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%11 = add nsw i32 %10, %8
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ret i32 %11
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}
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