mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37764 91177308-0d34-0410-b5e6-96231b3b80d8
693 lines
26 KiB
C++
693 lines
26 KiB
C++
//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass which is used
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// by the Linear Scan Register allocator. This pass linearizes the
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// basic blocks of the function in DFS order and uses the
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// LiveVariables pass to conservatively compute live intervals for
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// each virtual and physical register.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "liveintervals"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "VirtRegMap.h"
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#include "llvm/Value.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include <algorithm>
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#include <cmath>
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using namespace llvm;
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STATISTIC(numIntervals, "Number of original intervals");
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STATISTIC(numIntervalsAfter, "Number of intervals after coalescing");
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STATISTIC(numFolded , "Number of loads/stores folded into instructions");
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char LiveIntervals::ID = 0;
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namespace {
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RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis");
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}
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void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreserved<LiveVariables>();
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AU.addRequired<LiveVariables>();
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AU.addPreservedID(PHIEliminationID);
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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AU.addRequired<LoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void LiveIntervals::releaseMemory() {
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mi2iMap_.clear();
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i2miMap_.clear();
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r2iMap_.clear();
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}
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/// runOnMachineFunction - Register allocate the whole function
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///
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bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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tm_ = &fn.getTarget();
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mri_ = tm_->getRegisterInfo();
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tii_ = tm_->getInstrInfo();
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lv_ = &getAnalysis<LiveVariables>();
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allocatableRegs_ = mri_->getAllocatableSet(fn);
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// Number MachineInstrs and MachineBasicBlocks.
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// Initialize MBB indexes to a sentinal.
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MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U);
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unsigned MIIndex = 0;
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for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end();
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MBB != E; ++MBB) {
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// Set the MBB2IdxMap entry for this MBB.
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MBB2IdxMap[MBB->getNumber()] = MIIndex;
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second;
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assert(inserted && "multiple MachineInstr -> index mappings");
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i2miMap_.push_back(I);
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MIIndex += InstrSlots::NUM;
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}
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}
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computeIntervals();
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numIntervals += getNumIntervals();
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DOUT << "********** INTERVALS **********\n";
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for (iterator I = begin(), E = end(); I != E; ++I) {
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I->second.print(DOUT, mri_);
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DOUT << "\n";
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}
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numIntervalsAfter += getNumIntervals();
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DEBUG(dump());
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return true;
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}
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/// print - Implement the dump method.
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void LiveIntervals::print(std::ostream &O, const Module* ) const {
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O << "********** INTERVALS **********\n";
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for (const_iterator I = begin(), E = end(); I != E; ++I) {
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I->second.print(DOUT, mri_);
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DOUT << "\n";
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}
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O << "********** MACHINEINSTRS **********\n";
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for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
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mbbi != mbbe; ++mbbi) {
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O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
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for (MachineBasicBlock::iterator mii = mbbi->begin(),
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mie = mbbi->end(); mii != mie; ++mii) {
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O << getInstructionIndex(mii) << '\t' << *mii;
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}
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}
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}
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// Not called?
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/// CreateNewLiveInterval - Create a new live interval with the given live
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/// ranges. The new live interval will have an infinite spill weight.
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LiveInterval&
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LiveIntervals::CreateNewLiveInterval(const LiveInterval *LI,
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const std::vector<LiveRange> &LRs) {
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const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(LI->reg);
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// Create a new virtual register for the spill interval.
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unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(RC);
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// Replace the old virtual registers in the machine operands with the shiny
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// new one.
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for (std::vector<LiveRange>::const_iterator
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I = LRs.begin(), E = LRs.end(); I != E; ++I) {
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unsigned Index = getBaseIndex(I->start);
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unsigned End = getBaseIndex(I->end - 1) + InstrSlots::NUM;
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for (; Index != End; Index += InstrSlots::NUM) {
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// Skip deleted instructions
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while (Index != End && !getInstructionFromIndex(Index))
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Index += InstrSlots::NUM;
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if (Index == End) break;
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MachineInstr *MI = getInstructionFromIndex(Index);
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for (unsigned J = 0, e = MI->getNumOperands(); J != e; ++J) {
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MachineOperand &MOp = MI->getOperand(J);
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if (MOp.isRegister() && MOp.getReg() == LI->reg)
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MOp.setReg(NewVReg);
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}
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}
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}
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LiveInterval &NewLI = getOrCreateInterval(NewVReg);
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// The spill weight is now infinity as it cannot be spilled again
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NewLI.weight = float(HUGE_VAL);
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for (std::vector<LiveRange>::const_iterator
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I = LRs.begin(), E = LRs.end(); I != E; ++I) {
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DOUT << " Adding live range " << *I << " to new interval\n";
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NewLI.addRange(*I);
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}
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DOUT << "Created new live interval " << NewLI << "\n";
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return NewLI;
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}
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std::vector<LiveInterval*> LiveIntervals::
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addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
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// since this is called after the analysis is done we don't know if
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// LiveVariables is available
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lv_ = getAnalysisToUpdate<LiveVariables>();
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std::vector<LiveInterval*> added;
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assert(li.weight != HUGE_VALF &&
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"attempt to spill already spilled interval!");
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DOUT << "\t\t\t\tadding intervals for spills for interval: ";
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li.print(DOUT, mri_);
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DOUT << '\n';
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const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
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for (LiveInterval::Ranges::const_iterator
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i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
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unsigned index = getBaseIndex(i->start);
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unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM;
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for (; index != end; index += InstrSlots::NUM) {
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// skip deleted instructions
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while (index != end && !getInstructionFromIndex(index))
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index += InstrSlots::NUM;
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if (index == end) break;
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MachineInstr *MI = getInstructionFromIndex(index);
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RestartInstruction:
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for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
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MachineOperand& mop = MI->getOperand(i);
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if (mop.isRegister() && mop.getReg() == li.reg) {
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MachineInstr *fmi = li.remat ? NULL
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: mri_->foldMemoryOperand(MI, i, slot);
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if (fmi) {
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// Attempt to fold the memory reference into the instruction. If we
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// can do this, we don't need to insert spill code.
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if (lv_)
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lv_->instructionChanged(MI, fmi);
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MachineBasicBlock &MBB = *MI->getParent();
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vrm.virtFolded(li.reg, MI, i, fmi);
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mi2iMap_.erase(MI);
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i2miMap_[index/InstrSlots::NUM] = fmi;
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mi2iMap_[fmi] = index;
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MI = MBB.insert(MBB.erase(MI), fmi);
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++numFolded;
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// Folding the load/store can completely change the instruction in
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// unpredictable ways, rescan it from the beginning.
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goto RestartInstruction;
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} else {
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// Create a new virtual register for the spill interval.
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unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc);
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// Scan all of the operands of this instruction rewriting operands
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// to use NewVReg instead of li.reg as appropriate. We do this for
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// two reasons:
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//
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// 1. If the instr reads the same spilled vreg multiple times, we
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// want to reuse the NewVReg.
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// 2. If the instr is a two-addr instruction, we are required to
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// keep the src/dst regs pinned.
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//
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// Keep track of whether we replace a use and/or def so that we can
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// create the spill interval with the appropriate range.
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mop.setReg(NewVReg);
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bool HasUse = mop.isUse();
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bool HasDef = mop.isDef();
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for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
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if (MI->getOperand(j).isReg() &&
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MI->getOperand(j).getReg() == li.reg) {
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MI->getOperand(j).setReg(NewVReg);
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HasUse |= MI->getOperand(j).isUse();
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HasDef |= MI->getOperand(j).isDef();
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}
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}
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// create a new register for this spill
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vrm.grow();
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if (li.remat)
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vrm.setVirtIsReMaterialized(NewVReg, li.remat);
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vrm.assignVirt2StackSlot(NewVReg, slot);
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LiveInterval &nI = getOrCreateInterval(NewVReg);
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nI.remat = li.remat;
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assert(nI.empty());
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// the spill weight is now infinity as it
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// cannot be spilled again
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nI.weight = HUGE_VALF;
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if (HasUse) {
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LiveRange LR(getLoadIndex(index), getUseIndex(index),
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nI.getNextValue(~0U, 0));
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DOUT << " +" << LR;
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nI.addRange(LR);
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}
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if (HasDef) {
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LiveRange LR(getDefIndex(index), getStoreIndex(index),
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nI.getNextValue(~0U, 0));
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DOUT << " +" << LR;
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nI.addRange(LR);
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}
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added.push_back(&nI);
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// update live variables if it is available
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if (lv_)
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lv_->addVirtualRegisterKilled(NewVReg, MI);
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DOUT << "\t\t\t\tadded new interval: ";
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nI.print(DOUT, mri_);
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DOUT << '\n';
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}
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}
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}
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}
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}
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return added;
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}
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void LiveIntervals::printRegName(unsigned reg) const {
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if (MRegisterInfo::isPhysicalRegister(reg))
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cerr << mri_->getName(reg);
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else
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cerr << "%reg" << reg;
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}
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/// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to
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/// two addr elimination.
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static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
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const TargetInstrInfo *TII) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO1 = MI->getOperand(i);
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if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
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for (unsigned j = i+1; j < e; ++j) {
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MachineOperand &MO2 = MI->getOperand(j);
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if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
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MI->getInstrDescriptor()->
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getOperandConstraint(j, TOI::TIED_TO) == (int)i)
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return true;
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}
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}
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}
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return false;
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}
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void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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MachineBasicBlock::iterator mi,
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unsigned MIIdx,
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LiveInterval &interval) {
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DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
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LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
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// Virtual registers may be defined multiple times (due to phi
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// elimination and 2-addr elimination). Much of what we do only has to be
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// done once for the vreg. We use an empty interval to detect the first
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// time we see a vreg.
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if (interval.empty()) {
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// Remember if the definition can be rematerialized. All load's from fixed
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// stack slots are re-materializable. The target may permit other
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// instructions to be re-materialized as well.
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int FrameIdx = 0;
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if (vi.DefInst &&
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(tii_->isTriviallyReMaterializable(vi.DefInst) ||
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(tii_->isLoadFromStackSlot(vi.DefInst, FrameIdx) &&
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mf_->getFrameInfo()->isFixedObjectIndex(FrameIdx))))
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interval.remat = vi.DefInst;
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// Get the Idx of the defining instructions.
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unsigned defIndex = getDefIndex(MIIdx);
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unsigned ValNum;
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unsigned SrcReg, DstReg;
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if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
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ValNum = interval.getNextValue(~0U, 0);
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else
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ValNum = interval.getNextValue(defIndex, SrcReg);
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assert(ValNum == 0 && "First value in interval is not 0?");
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ValNum = 0; // Clue in the optimizer.
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// Loop over all of the blocks that the vreg is defined in. There are
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// two cases we have to handle here. The most common case is a vreg
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// whose lifetime is contained within a basic block. In this case there
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// will be a single kill, in MBB, which comes after the definition.
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if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
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// FIXME: what about dead vars?
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unsigned killIdx;
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if (vi.Kills[0] != mi)
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killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1;
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else
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killIdx = defIndex+1;
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// If the kill happens after the definition, we have an intra-block
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// live range.
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if (killIdx > defIndex) {
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assert(vi.AliveBlocks.none() &&
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"Shouldn't be alive across any blocks!");
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LiveRange LR(defIndex, killIdx, ValNum);
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interval.addRange(LR);
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DOUT << " +" << LR << "\n";
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return;
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}
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}
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// The other case we handle is when a virtual register lives to the end
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// of the defining block, potentially live across some blocks, then is
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// live into some number of blocks, but gets killed. Start by adding a
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// range that goes from this definition to the end of the defining block.
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LiveRange NewLR(defIndex,
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getInstructionIndex(&mbb->back()) + InstrSlots::NUM,
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ValNum);
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DOUT << " +" << NewLR;
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interval.addRange(NewLR);
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// Iterate over all of the blocks that the variable is completely
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// live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
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// live interval.
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for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) {
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if (vi.AliveBlocks[i]) {
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MachineBasicBlock *MBB = mf_->getBlockNumbered(i);
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if (!MBB->empty()) {
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LiveRange LR(getMBBStartIdx(i),
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getInstructionIndex(&MBB->back()) + InstrSlots::NUM,
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ValNum);
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interval.addRange(LR);
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DOUT << " +" << LR;
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}
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}
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}
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// Finally, this virtual register is live from the start of any killing
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// block to the 'use' slot of the killing instruction.
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for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
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MachineInstr *Kill = vi.Kills[i];
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LiveRange LR(getMBBStartIdx(Kill->getParent()),
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getUseIndex(getInstructionIndex(Kill))+1,
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ValNum);
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interval.addRange(LR);
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DOUT << " +" << LR;
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}
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} else {
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// Can no longer safely assume definition is rematerializable.
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interval.remat = NULL;
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// If this is the second time we see a virtual register definition, it
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// must be due to phi elimination or two addr elimination. If this is
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// the result of two address elimination, then the vreg is one of the
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// def-and-use register operand.
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if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) {
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// If this is a two-address definition, then we have already processed
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// the live range. The only problem is that we didn't realize there
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// are actually two values in the live interval. Because of this we
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// need to take the LiveRegion that defines this register and split it
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// into two values.
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unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst));
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unsigned RedefIndex = getDefIndex(MIIdx);
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// Delete the initial value, which should be short and continuous,
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// because the 2-addr copy must be in the same MBB as the redef.
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interval.removeRange(DefIndex, RedefIndex);
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// Two-address vregs should always only be redefined once. This means
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// that at this point, there should be exactly one value number in it.
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assert(interval.containsOneValue() && "Unexpected 2-addr liveint!");
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// The new value number (#1) is defined by the instruction we claimed
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// defined value #0.
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unsigned ValNo = interval.getNextValue(0, 0);
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interval.setValueNumberInfo(1, interval.getValNumInfo(0));
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// Value#0 is now defined by the 2-addr instruction.
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interval.setValueNumberInfo(0, std::make_pair(~0U, 0U));
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// Add the new live interval which replaces the range for the input copy.
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LiveRange LR(DefIndex, RedefIndex, ValNo);
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DOUT << " replace range with " << LR;
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interval.addRange(LR);
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// If this redefinition is dead, we need to add a dummy unit live
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// range covering the def slot.
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if (lv_->RegisterDefIsDead(mi, interval.reg))
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interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
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DOUT << " RESULT: ";
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interval.print(DOUT, mri_);
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} else {
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// Otherwise, this must be because of phi elimination. If this is the
|
|
// first redefinition of the vreg that we have seen, go back and change
|
|
// the live range in the PHI block to be a different value number.
|
|
if (interval.containsOneValue()) {
|
|
assert(vi.Kills.size() == 1 &&
|
|
"PHI elimination vreg should have one kill, the PHI itself!");
|
|
|
|
// Remove the old range that we now know has an incorrect number.
|
|
MachineInstr *Killer = vi.Kills[0];
|
|
unsigned Start = getMBBStartIdx(Killer->getParent());
|
|
unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
|
|
DOUT << " Removing [" << Start << "," << End << "] from: ";
|
|
interval.print(DOUT, mri_); DOUT << "\n";
|
|
interval.removeRange(Start, End);
|
|
DOUT << " RESULT: "; interval.print(DOUT, mri_);
|
|
|
|
// Replace the interval with one of a NEW value number. Note that this
|
|
// value number isn't actually defined by an instruction, weird huh? :)
|
|
LiveRange LR(Start, End, interval.getNextValue(~0U, 0));
|
|
DOUT << " replace range with " << LR;
|
|
interval.addRange(LR);
|
|
DOUT << " RESULT: "; interval.print(DOUT, mri_);
|
|
}
|
|
|
|
// In the case of PHI elimination, each variable definition is only
|
|
// live until the end of the block. We've already taken care of the
|
|
// rest of the live range.
|
|
unsigned defIndex = getDefIndex(MIIdx);
|
|
|
|
unsigned ValNum;
|
|
unsigned SrcReg, DstReg;
|
|
if (!tii_->isMoveInstr(*mi, SrcReg, DstReg))
|
|
ValNum = interval.getNextValue(~0U, 0);
|
|
else
|
|
ValNum = interval.getNextValue(defIndex, SrcReg);
|
|
|
|
LiveRange LR(defIndex,
|
|
getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum);
|
|
interval.addRange(LR);
|
|
DOUT << " +" << LR;
|
|
}
|
|
}
|
|
|
|
DOUT << '\n';
|
|
}
|
|
|
|
void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator mi,
|
|
unsigned MIIdx,
|
|
LiveInterval &interval,
|
|
unsigned SrcReg) {
|
|
// A physical register cannot be live across basic block, so its
|
|
// lifetime must end somewhere in its defining basic block.
|
|
DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
|
|
|
|
unsigned baseIndex = MIIdx;
|
|
unsigned start = getDefIndex(baseIndex);
|
|
unsigned end = start;
|
|
|
|
// If it is not used after definition, it is considered dead at
|
|
// the instruction defining it. Hence its interval is:
|
|
// [defSlot(def), defSlot(def)+1)
|
|
if (lv_->RegisterDefIsDead(mi, interval.reg)) {
|
|
DOUT << " dead";
|
|
end = getDefIndex(start) + 1;
|
|
goto exit;
|
|
}
|
|
|
|
// If it is not dead on definition, it must be killed by a
|
|
// subsequent instruction. Hence its interval is:
|
|
// [defSlot(def), useSlot(kill)+1)
|
|
while (++mi != MBB->end()) {
|
|
baseIndex += InstrSlots::NUM;
|
|
if (lv_->KillsRegister(mi, interval.reg)) {
|
|
DOUT << " killed";
|
|
end = getUseIndex(baseIndex) + 1;
|
|
goto exit;
|
|
} else if (lv_->ModifiesRegister(mi, interval.reg)) {
|
|
// Another instruction redefines the register before it is ever read.
|
|
// Then the register is essentially dead at the instruction that defines
|
|
// it. Hence its interval is:
|
|
// [defSlot(def), defSlot(def)+1)
|
|
DOUT << " dead";
|
|
end = getDefIndex(start) + 1;
|
|
goto exit;
|
|
}
|
|
}
|
|
|
|
// The only case we should have a dead physreg here without a killing or
|
|
// instruction where we know it's dead is if it is live-in to the function
|
|
// and never used.
|
|
assert(!SrcReg && "physreg was not killed in defining block!");
|
|
end = getDefIndex(start) + 1; // It's dead.
|
|
|
|
exit:
|
|
assert(start < end && "did not find end of interval?");
|
|
|
|
// Already exists? Extend old live interval.
|
|
LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start);
|
|
unsigned Id = (OldLR != interval.end())
|
|
? OldLR->ValId
|
|
: interval.getNextValue(SrcReg != 0 ? start : ~0U, SrcReg);
|
|
LiveRange LR(start, end, Id);
|
|
interval.addRange(LR);
|
|
DOUT << " +" << LR << '\n';
|
|
}
|
|
|
|
void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
unsigned MIIdx,
|
|
unsigned reg) {
|
|
if (MRegisterInfo::isVirtualRegister(reg))
|
|
handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg));
|
|
else if (allocatableRegs_[reg]) {
|
|
unsigned SrcReg, DstReg;
|
|
if (!tii_->isMoveInstr(*MI, SrcReg, DstReg))
|
|
SrcReg = 0;
|
|
handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg);
|
|
// Def of a register also defines its sub-registers.
|
|
for (const unsigned* AS = mri_->getSubRegisters(reg); *AS; ++AS)
|
|
// Avoid processing some defs more than once.
|
|
if (!MI->findRegisterDefOperand(*AS))
|
|
handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0);
|
|
}
|
|
}
|
|
|
|
void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
|
|
unsigned MIIdx,
|
|
LiveInterval &interval, bool isAlias) {
|
|
DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg));
|
|
|
|
// Look for kills, if it reaches a def before it's killed, then it shouldn't
|
|
// be considered a livein.
|
|
MachineBasicBlock::iterator mi = MBB->begin();
|
|
unsigned baseIndex = MIIdx;
|
|
unsigned start = baseIndex;
|
|
unsigned end = start;
|
|
while (mi != MBB->end()) {
|
|
if (lv_->KillsRegister(mi, interval.reg)) {
|
|
DOUT << " killed";
|
|
end = getUseIndex(baseIndex) + 1;
|
|
goto exit;
|
|
} else if (lv_->ModifiesRegister(mi, interval.reg)) {
|
|
// Another instruction redefines the register before it is ever read.
|
|
// Then the register is essentially dead at the instruction that defines
|
|
// it. Hence its interval is:
|
|
// [defSlot(def), defSlot(def)+1)
|
|
DOUT << " dead";
|
|
end = getDefIndex(start) + 1;
|
|
goto exit;
|
|
}
|
|
|
|
baseIndex += InstrSlots::NUM;
|
|
++mi;
|
|
}
|
|
|
|
exit:
|
|
// Live-in register might not be used at all.
|
|
if (end == MIIdx) {
|
|
if (isAlias) {
|
|
DOUT << " dead";
|
|
end = getDefIndex(MIIdx) + 1;
|
|
} else {
|
|
DOUT << " live through";
|
|
end = baseIndex;
|
|
}
|
|
}
|
|
|
|
LiveRange LR(start, end, interval.getNextValue(~0U, 0));
|
|
DOUT << " +" << LR << '\n';
|
|
interval.addRange(LR);
|
|
}
|
|
|
|
/// computeIntervals - computes the live intervals for virtual
|
|
/// registers. for some ordering of the machine instructions [1,N] a
|
|
/// live interval is an interval [i, j) where 1 <= i <= j < N for
|
|
/// which a variable is live
|
|
void LiveIntervals::computeIntervals() {
|
|
DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
|
|
<< "********** Function: "
|
|
<< ((Value*)mf_->getFunction())->getName() << '\n';
|
|
// Track the index of the current machine instr.
|
|
unsigned MIIndex = 0;
|
|
for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
|
|
MBBI != E; ++MBBI) {
|
|
MachineBasicBlock *MBB = MBBI;
|
|
DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
|
|
|
|
MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
|
|
|
|
if (MBB->livein_begin() != MBB->livein_end()) {
|
|
// Create intervals for live-ins to this BB first.
|
|
for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(),
|
|
LE = MBB->livein_end(); LI != LE; ++LI) {
|
|
handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
|
|
// Multiple live-ins can alias the same register.
|
|
for (const unsigned* AS = mri_->getSubRegisters(*LI); *AS; ++AS)
|
|
if (!hasInterval(*AS))
|
|
handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS),
|
|
true);
|
|
}
|
|
}
|
|
|
|
for (; MI != miEnd; ++MI) {
|
|
DOUT << MIIndex << "\t" << *MI;
|
|
|
|
// Handle defs.
|
|
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
// handle register defs - build intervals
|
|
if (MO.isRegister() && MO.getReg() && MO.isDef())
|
|
handleRegisterDef(MBB, MI, MIIndex, MO.getReg());
|
|
}
|
|
|
|
MIIndex += InstrSlots::NUM;
|
|
}
|
|
}
|
|
}
|
|
|
|
LiveInterval LiveIntervals::createInterval(unsigned reg) {
|
|
float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
|
|
HUGE_VALF : 0.0F;
|
|
return LiveInterval(reg, Weight);
|
|
}
|